GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
coreboot-kgpe-d16/src/soc/intel/alderlake/chip.c

179 lines
4.8 KiB
C
Raw Normal View History

soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 08:00:58 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/acpi.h>
#include <intelblocks/cfg.h>
soc/intel: hook up new gpio device in the soc chips This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 22:13:44 +01:00
#include <intelblocks/gpio.h>
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 08:00:58 +02:00
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
soc/intel/alderlake: Update PCH and CPU PCIe RP table According ADL EDS to update the PCH and CPU PCIe RP table. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-31 04:43:29 +01:00
#include <soc/pcie.h>
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 08:00:58 +02:00
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
#if CONFIG(HAVE_ACPI_TABLES)
const char *soc_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
return "PCI0";
if (dev->path.type == DEVICE_PATH_USB) {
switch (dev->path.usb.port_type) {
case 0:
/* Root Hub */
return "RHUB";
case 2:
/* USB2 ports */
switch (dev->path.usb.port_id) {
case 0: return "HS01";
case 1: return "HS02";
case 2: return "HS03";
case 3: return "HS04";
case 4: return "HS05";
case 5: return "HS06";
case 6: return "HS07";
case 7: return "HS08";
case 8: return "HS09";
case 9: return "HS10";
}
break;
case 3:
/* USB3 ports */
switch (dev->path.usb.port_id) {
case 0: return "SS01";
case 1: return "SS02";
case 2: return "SS03";
case 3: return "SS04";
}
break;
}
return NULL;
}
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
case SA_DEVFN_TCSS_XHCI: return "TXHC";
case SA_DEVFN_TCSS_XDCI: return "TXDC";
case SA_DEVFN_TCSS_DMA0: return "TDM0";
case SA_DEVFN_TCSS_DMA1: return "TDM1";
case SA_DEVFN_TBT0: return "TRP0";
case SA_DEVFN_TBT1: return "TRP1";
case SA_DEVFN_TBT2: return "TRP2";
case SA_DEVFN_TBT3: return "TRP3";
case SA_DEVFN_IPU: return "IPU0";
case PCH_DEVFN_ISH: return "ISHB";
case PCH_DEVFN_XHCI: return "XHCI";
case PCH_DEVFN_I2C0: return "I2C0";
case PCH_DEVFN_I2C1: return "I2C1";
case PCH_DEVFN_I2C2: return "I2C2";
case PCH_DEVFN_I2C3: return "I2C3";
case PCH_DEVFN_I2C4: return "I2C4";
case PCH_DEVFN_I2C5: return "I2C5";
case PCH_DEVFN_SATA: return "SATA";
case PCH_DEVFN_PCIE1: return "RP01";
case PCH_DEVFN_PCIE2: return "RP02";
case PCH_DEVFN_PCIE3: return "RP03";
case PCH_DEVFN_PCIE4: return "RP04";
case PCH_DEVFN_PCIE5: return "RP05";
case PCH_DEVFN_PCIE6: return "RP06";
case PCH_DEVFN_PCIE7: return "RP07";
case PCH_DEVFN_PCIE8: return "RP08";
case PCH_DEVFN_PCIE9: return "RP09";
case PCH_DEVFN_PCIE10: return "RP10";
case PCH_DEVFN_PCIE11: return "RP11";
case PCH_DEVFN_PCIE12: return "RP12";
case PCH_DEVFN_PMC: return "PMC";
case PCH_DEVFN_UART0: return "UAR0";
case PCH_DEVFN_UART1: return "UAR1";
case PCH_DEVFN_UART2: return "UAR2";
case PCH_DEVFN_GSPI0: return "SPI0";
case PCH_DEVFN_GSPI1: return "SPI1";
case PCH_DEVFN_GSPI2: return "SPI2";
case PCH_DEVFN_GSPI3: return "SPI3";
/* Keeping ACPI device name coherent with ec.asl */
case PCH_DEVFN_ESPI: return "LPCB";
case PCH_DEVFN_HDA: return "HDAS";
case PCH_DEVFN_SMBUS: return "SBUS";
case PCH_DEVFN_GBE: return "GLAN";
}
return NULL;
}
#endif
/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
static void soc_fill_gpio_pm_configuration(void)
{
uint8_t value[TOTAL_GPIO_COMM];
const config_t *config = config_of_soc();
if (config->gpio_override_pm)
soc/intel: Replace open-coded buffer length calculation Use `sizeof(value)` instead of manually calculating the buffer size. Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:02:45 +02:00
memcpy(value, config->gpio_pm, sizeof(value));
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 08:00:58 +02:00
else
soc/intel: Replace open-coded buffer length calculation Use `sizeof(value)` instead of manually calculating the buffer size. Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:02:45 +02:00
memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 08:00:58 +02:00
gpio_pm_configure(value, TOTAL_GPIO_COMM);
}
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
soc/amd,intel: Drop s3_resume parameter on FSP-S functions ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-09 21:53:52 +01:00
fsp_silicon_init();
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 08:00:58 +02:00
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
soc_fill_gpio_pm_configuration();
/* Swap enabled PCI ports in device tree if needed. */
soc/intel/alderlake: Update PCH and CPU PCIe RP table According ADL EDS to update the PCH and CPU PCIe RP table. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-31 04:43:29 +01:00
pcie_rp_update_devicetree(get_pch_pcie_rp_table());
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 08:00:58 +02:00
}
static struct device_operations pci_domain_ops = {
.read_resources = &pci_domain_read_resources,
.set_resources = &pci_domain_set_resources,
.scan_bus = &pci_domain_scan_bus,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = &soc_acpi_name,
#endif
};
static struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt = generate_cpu_entries,
#endif
};
static void soc_enable(struct device *dev)
{
/*
* Set the operations if it is a special bus type or a hidden PCI
* device.
*/
if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
else if (dev->path.type == DEVICE_PATH_PCI &&
dev->path.pci.devfn == PCH_DEVFN_PMC)
dev->ops = &pmc_ops;
soc/intel: hook up new gpio device in the soc chips This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 22:13:44 +01:00
else if (dev->path.type == DEVICE_PATH_GPIO)
block_gpio_enable(dev);
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 08:00:58 +02:00
}
struct chip_operations soc_intel_alderlake_ops = {
CHIP_NAME("Intel Alderlake")
.enable_dev = &soc_enable,
.init = &soc_init_pre_device,
};
Reference in a new issue Copy permalink