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Documentation/releases: Add 4.15 release notes template Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-10 23:24:07 +02:00
Upcoming release - coreboot 4.15
================================
Documentation/releases: Update 4.15 release notes Update details for upcoming 4.15 release Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I4517f7c17ce5788c82a1eafb1589e39b1ce403ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58422 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18 16:04:09 +02:00
The 4.15 release is planned for November 1st, 2021.
Documentation/releases: Add 4.15 release notes template Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-10 23:24:07 +02:00
Documentation/releases: Update 4.15 release notes Update details for upcoming 4.15 release Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I4517f7c17ce5788c82a1eafb1589e39b1ce403ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58422 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18 16:04:09 +02:00
Since 4.14 there have been more than 2448 new commits by more than 219 developers.
Of these, over 73 contributed to coreboot for the first time.
Documentation/releases: Add 4.15 release notes template Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-10 23:24:07 +02:00
Documentation/releases: Update 4.15 release notes Update details for upcoming 4.15 release Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I4517f7c17ce5788c82a1eafb1589e39b1ce403ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58422 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18 16:04:09 +02:00
Welcome to the project!
Thank you to all the developers who continue to make coreboot the
great open source firmware project that it is.
New mainboards
--------------
* Asus p8h61-m_pro_cm6630
* Asus p8h77-v
* Asus p8z77-v
* Google nipperkin
* Lenovo w541
* Siemens mc_ehl
* SuperMicro x9sae
* System76 addw1
* System76 darp6
* System76 darp7
* System76 galp4
* System76 galp5
* System76 lemp10
Removed mainboards
------------------
* Google Mancomb
Deprecations and incompatible changes
-------------------------------------
### COREBOOTPAYLOAD option
Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
option since it applied only to CorebootPayloadPkg. Clean up the Makefile now
that we're only building from a single Tianocore package/target.
### Remove old lp4x and ddr4 versions of spd_tools
The migration to the new unified version of spd_tools is complete, so
the old lp4x and ddr4 versions can be removed.
### Remove AMD PI 00630F01
No board currently uses AMD PI 00630F01 so remove it.
Documentation/releases: Add 4.15 release notes template Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-10 23:24:07 +02:00
Significant changes
-------------------
Doc/releases: Mention that Asus H61 boards got squashed Not physically squashed, the coreboot code got turned into a variant setup with override devicetrees to drop redundant boilerplate. Change-Id: I7ae5530d2603d6d108ef3829004de7e1cad130f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-19 23:07:08 +02:00
### Merged family of Asus mainboards using H61 chipset
By using newer coreboot features like board variants and override devicetrees,
lots of code can now be shared. This should ease maintenance and also make it
easier for newcomers to add support for even more mainboards.
soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-13 08:31:52 +02:00
### Changed default setting for Intel chipset lockdown
Previously, the default behaviour for Intel chipset lockdown was to let the FSP
do it. Since all related mainboards used the coreboot mechanisms for chipset
lockdown, the default behaviour was changed to that.
Documentation/releases/4.15: Add note about libpayload improvements Change-Id: I3043e70523db1b7f1df90789a69eadd155848bb0 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-10-21 12:54:36 +02:00
### Payloads unit testing
Libpayload now supports the mock architecture, which can be used for unit testing
payloads. (For examples see
[depthcharge](https://chromium.googlesource.com/chromiumos/platform/depthcharge/)
payload)
### Unit testing infrastructure
Unit testing of libpayload is now possible in the same fashion as in the main
coreboot tree.
soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-13 08:31:52 +02:00
Documentation/releases: Update 4.15 release notes Update details for upcoming 4.15 release Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I4517f7c17ce5788c82a1eafb1589e39b1ce403ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58422 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18 16:04:09 +02:00
### Introduce new method for accessing cpu_info
There is currently a fundamental flaw in the current cpu_info()
implementation. It assumes that current stack is CONFIG_STACK_SIZE
aligned. This assumption breaks down when performing SMM relocation.
The first step in performing SMM relocation is changing the SMBASE. This
is accomplished by installing the smmstub at 0x00038000, which is the
default SMM entry point. The stub is configured to set up a new stack
with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point
of smm_do_relocation located in RAMSTAGE RAM.
This means that when smm_do_relocation is executed, it is running in SMM
with a different sized stack. When cpu_info() gets called it will be
using CONFIG_STACK_SIZE to calculate the location of the cpu_info
struct. This results in reading random memory. Since cpu_info() has to
run in multiple environments, we can't use a compile time constant to
locate the cpu_info struct.
This CL introduces a new way of locating cpu_info. It uses a per-cpu
segment descriptor that points to a per-cpu segment that is allocated on
the stack. By using a segment descriptor to point to the per-cpu data,
we no longer need to calculate the location of the cpu_info struct. This
has the following advantages:
* Stacks no longer need to be CONFIG_STACK_SIZE aligned.
* Accessing an unconfigured segment will result in an exception. This
ensures no one can call cpu_info() from an unsupported environment.
* Segment selectors are cleared when entering SMM and restored when
leaving SMM.
* There is a 1:1 mapping between cpu and cpu_info. When using
COOP_MULTITASKING, a new cpu_info is currently allocated at the top of
each thread's stack. This no longer needs to happen.