44 lines
1.4 KiB
Plaintext
44 lines
1.4 KiB
Plaintext
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 VIA Technologies, Inc.
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## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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target via_epia_n
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mainboard via/epia-n
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option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=10
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option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=10
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option CONFIG_CONSOLE_SERIAL8250=1
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# coreboot C code runs at this location in RAM
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option CONFIG_RAMBASE=0x00004000
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#
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# Generate the final ROM like this:
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# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
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#
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#option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
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romimage "fallback"
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option COREBOOT_EXTRA_VERSION = "-epia_n-fallback"
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payload ../../../../../payloads/filo/build/filo.elf
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end
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buildrom ./coreboot.rom CONFIG_FALLBACK_SIZE "fallback"
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