616 lines
15 KiB
C
616 lines
15 KiB
C
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/*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/* This file is derived from the flashrom project. */
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bootstate.h>
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#include <delay.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <spi_flash.h>
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#include <spi-generic.h>
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#include <soc/pci_devs.h>
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#include <soc/spi.h>
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#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
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#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
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#define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_OFF)
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#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
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#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
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#if ENV_SMM
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#define pci_read_config_byte(dev, reg, targ)\
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(*(targ) = pci_read_config8(dev, reg))
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#define pci_read_config_word(dev, reg, targ)\
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(*(targ) = pci_read_config16(dev, reg))
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#define pci_read_config_dword(dev, reg, targ)\
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(*(targ) = pci_read_config32(dev, reg))
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#define pci_write_config_byte(dev, reg, val)\
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pci_write_config8(dev, reg, val)
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#define pci_write_config_word(dev, reg, val)\
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pci_write_config16(dev, reg, val)
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#define pci_write_config_dword(dev, reg, val)\
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pci_write_config32(dev, reg, val)
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#else /* !ENV_SMM */
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#include <device/device.h>
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#include <device/pci.h>
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#define pci_read_config_byte(dev, reg, targ)\
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(*(targ) = pci_read_config8(dev, reg))
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#define pci_read_config_word(dev, reg, targ)\
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(*(targ) = pci_read_config16(dev, reg))
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#define pci_read_config_dword(dev, reg, targ)\
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(*(targ) = pci_read_config32(dev, reg))
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#define pci_write_config_byte(dev, reg, val)\
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pci_write_config8(dev, reg, val)
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#define pci_write_config_word(dev, reg, val)\
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pci_write_config16(dev, reg, val)
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#define pci_write_config_dword(dev, reg, val)\
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pci_write_config32(dev, reg, val)
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#endif /* ENV_SMM */
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#define B_PCH_SPI_BAR0_MASK 0x0FFF
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typedef struct spi_slave pch_spi_slave;
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static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi);
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static int pch_hwseq_write(struct spi_flash *flash,
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u32 addr, size_t len, const void *buf);
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static int pch_hwseq_read(struct spi_flash *flash,
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u32 addr, size_t len, void *buf);
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typedef struct pch_spi_regs {
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uint32_t bfpr;
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uint16_t hsfs;
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uint16_t hsfc;
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uint32_t faddr;
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uint32_t _reserved0;
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uint32_t fdata[16];
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uint32_t frap;
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uint32_t freg[6];
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uint32_t _reserved1[6];
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uint32_t pr[5];
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uint32_t _reserved2[2];
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uint8_t ssfs;
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uint8_t ssfc[3];
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uint16_t preop;
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uint16_t optype;
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uint8_t opmenu[8];
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uint32_t bbar;
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uint32_t fdoc;
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uint32_t fdod;
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uint8_t _reserved4[8];
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uint32_t afc;
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uint32_t lvscc;
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uint32_t uvscc;
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uint8_t _reserved5[4];
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uint32_t fpb;
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uint8_t _reserved6[28];
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uint32_t srdl;
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uint32_t srdc;
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uint32_t srd;
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} __attribute__((packed)) pch_spi_regs;
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typedef struct pch_spi_controller {
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int locked;
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uint32_t flmap0;
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uint32_t hsfs;
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pch_spi_regs *pch_spi;
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uint8_t *opmenu;
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int menubytes;
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uint16_t *preop;
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uint16_t *optype;
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uint32_t *addr;
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uint8_t *data;
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unsigned databytes;
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uint8_t *status;
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uint16_t *control;
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uint32_t *bbar;
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} pch_spi_controller;
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static pch_spi_controller cntlr;
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enum {
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HSFS_FDONE = 0x0001,
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HSFS_FCERR = 0x0002,
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HSFS_AEL = 0x0004,
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HSFS_BERASE_MASK = 0x0018,
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HSFS_BERASE_SHIFT = 3,
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HSFS_SCIP = 0x0020,
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HSFS_FDOPSS = 0x2000,
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HSFS_FDV = 0x4000,
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HSFS_FLOCKDN = 0x8000
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};
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enum {
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HSFC_FGO = 0x0001,
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HSFC_FCYCLE_MASK = 0x0006,
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HSFC_FCYCLE_SHIFT = 1,
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HSFC_FDBC_MASK = 0x3f00,
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HSFC_FDBC_SHIFT = 8,
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HSFC_FSMIE = 0x8000
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};
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#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
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static u8 readb_(const void *addr)
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{
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u8 v = read8(addr);
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printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
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v, ((unsigned) addr & 0xffff) - 0xf020);
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return v;
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}
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static u16 readw_(const void *addr)
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{
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u16 v = read16(addr);
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printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
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v, ((unsigned) addr & 0xffff) - 0xf020);
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return v;
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}
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static u32 readl_(const void *addr)
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{
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u32 v = read32(addr);
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printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
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v, ((unsigned) addr & 0xffff) - 0xf020);
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return v;
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}
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static void writeb_(u8 b, void *addr)
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{
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write8(addr, b);
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printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
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b, ((unsigned) addr & 0xffff) - 0xf020);
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}
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static void writew_(u16 b, void *addr)
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{
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write16(addr, b);
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printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
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b, ((unsigned) addr & 0xffff) - 0xf020);
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}
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static void writel_(u32 b, void *addr)
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{
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write32(addr, b);
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printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
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b, ((unsigned) addr & 0xffff) - 0xf020);
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}
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#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
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#define readb_(a) read8(a)
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#define readw_(a) read16(a)
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#define readl_(a) read32(a)
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#define writeb_(val, addr) write8(addr, val)
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#define writew_(val, addr) write16(addr, val)
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#define writel_(val, addr) write32(addr, val)
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#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
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static void pch_set_bbar(uint32_t minaddr)
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{
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uint32_t pchspi_bbar;
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minaddr &= SPIBAR_MEMBAR_MASK;
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pchspi_bbar = readl_(cntlr.bbar) & ~SPIBAR_MEMBAR_MASK;
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pchspi_bbar |= minaddr;
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writel_(pchspi_bbar, cntlr.bbar);
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}
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unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
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{
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return min(cntlr.databytes, buf_len);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
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{
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pch_spi_slave *slave = malloc(sizeof(*slave));
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if (!slave) {
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printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n");
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return NULL;
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}
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memset(slave, 0, sizeof(*slave));
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slave->bus = bus;
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slave->cs = cs;
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slave->force_programmer_specific = 1;
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slave->programmer_specific_probe = spi_flash_hwseq_probe;
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return slave;
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}
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static u32 spi_get_flash_size(void)
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{
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uint32_t flcomp;
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u32 size;
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writel_(SPIBAR_FDOC_COMPONENT, &cntlr.pch_spi->fdoc);
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flcomp = readl_(&cntlr.pch_spi->fdod);
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printk(BIOS_DEBUG, "flcomp = %x\n", flcomp);
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switch (flcomp & FLCOMP_C0DEN_MASK) {
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case FLCOMP_C0DEN_8MB:
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size = 0x100000;
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break;
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case FLCOMP_C0DEN_16MB:
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size = 0x1000000;
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break;
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case FLCOMP_C0DEN_32MB:
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size = 0x10000000;
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break;
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default:
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size = 0x1000000;
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}
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printk(BIOS_DEBUG, "flash size 0x%x bytes\n", size);
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return size;
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}
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int spi_xfer(struct spi_slave *slave, const void *dout,
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unsigned int bytesout, void *din, unsigned int bytesin)
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{
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/* TODO: Define xfer for hardware sequencing. */
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return -1;
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}
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void spi_init(void)
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{
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uint8_t bios_cntl;
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device_t dev = PCH_DEV_SPI;
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pch_spi_regs *pch_spi;
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uint16_t hsfs;
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/* Root Complex Register Block */
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pch_spi = (pch_spi_regs *)(get_spi_bar());
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cntlr.pch_spi = pch_spi;
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hsfs = readw_(&pch_spi->hsfs);
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cntlr.hsfs = hsfs;
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cntlr.opmenu = pch_spi->opmenu;
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cntlr.menubytes = sizeof(pch_spi->opmenu);
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cntlr.optype = &pch_spi->optype;
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cntlr.addr = &pch_spi->faddr;
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cntlr.data = (uint8_t *)pch_spi->fdata;
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cntlr.databytes = sizeof(pch_spi->fdata);
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cntlr.status = &pch_spi->ssfs;
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cntlr.control = (uint16_t *)pch_spi->ssfc;
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cntlr.bbar = &pch_spi->bbar;
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cntlr.preop = &pch_spi->preop;
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if (cntlr.hsfs & HSFS_FDV) {
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/* Select Flash Descriptor Section Index to 1 */
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writel_(SPIBAR_FDOC_FDSI_1, &pch_spi->fdoc);
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cntlr.flmap0 = readl_(&pch_spi->fdod);
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}
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pch_set_bbar(0);
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/* Disable the BIOS write protect so write commands are allowed. */
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pci_read_config_byte(dev, SPIBAR_BIOS_CNTL, &bios_cntl);
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bios_cntl &= ~SPIBAR_BC_EISS;
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bios_cntl |= SPIBAR_BC_WPD;
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pci_write_config_byte(dev, SPIBAR_BIOS_CNTL, bios_cntl);
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}
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#if ENV_RAMSTAGE
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static void spi_init_cb(void *unused)
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{
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spi_init();
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
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#endif /* ENV_RAMSTAGE */
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int spi_claim_bus(struct spi_slave *slave)
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{
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/* Handled by PCH automatically. */
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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/* Handled by PCH automatically. */
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}
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static void pch_hwseq_set_addr(uint32_t addr)
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{
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uint32_t addr_old = readl_(&cntlr.pch_spi->faddr) & ~SPIBAR_FADDR_MASK;
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writel_((addr & SPIBAR_FADDR_MASK) | addr_old, &cntlr.pch_spi->faddr);
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}
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/*
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* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
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* Resets all error flags in HSFS.
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* Returns 0 if the cycle completes successfully without errors within
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* timeout us, 1 on errors.
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*/
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static int pch_hwseq_wait_for_cycle_complete(unsigned int timeout,
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unsigned int len)
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{
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uint16_t hsfs;
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uint32_t addr;
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timeout /= 8; /* scale timeout duration to counter */
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while ((((hsfs = readw_(&cntlr.pch_spi->hsfs)) &
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(HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) {
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udelay(8);
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}
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writew_(readw_(&cntlr.pch_spi->hsfs), &cntlr.pch_spi->hsfs);
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if (!timeout) {
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uint16_t hsfc;
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addr = readl_(&cntlr.pch_spi->faddr) & SPIBAR_FADDR_MASK;
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hsfc = readw_(&cntlr.pch_spi->hsfc);
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printk(BIOS_ERR, "Transaction timeout between offset 0x%08x \
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and 0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
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addr, addr + len - 1, addr, len - 1,
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hsfc, hsfs);
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return 1;
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}
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if (hsfs & HSFS_FCERR) {
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uint16_t hsfc;
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addr = readl_(&cntlr.pch_spi->faddr) & SPIBAR_FADDR_MASK;
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hsfc = readw_(&cntlr.pch_spi->hsfc);
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printk(BIOS_ERR, "Transaction error between offset 0x%08x and \
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0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
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addr, addr + len - 1, addr, len - 1,
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hsfc, hsfs);
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return 1;
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}
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return 0;
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}
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static int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
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{
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u32 start, end, erase_size;
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int ret;
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uint16_t hsfc;
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uint16_t timeout = 1000 * 60;
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erase_size = flash->sector_size;
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if (offset % erase_size || len % erase_size) {
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printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
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return -1;
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}
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flash->spi->rw = SPI_WRITE_FLAG;
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ret = spi_claim_bus(flash->spi);
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if (ret) {
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printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
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return ret;
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}
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|
|
||
|
start = offset;
|
||
|
end = start + len;
|
||
|
|
||
|
while (offset < end) {
|
||
|
/*
|
||
|
* Make sure FDONE, FCERR, AEL are
|
||
|
* cleared by writing 1 to them.
|
||
|
*/
|
||
|
writew_(readw_(&cntlr.pch_spi->hsfs), &cntlr.pch_spi->hsfs);
|
||
|
|
||
|
pch_hwseq_set_addr(offset);
|
||
|
|
||
|
offset += erase_size;
|
||
|
|
||
|
hsfc = readw_(&cntlr.pch_spi->hsfc);
|
||
|
hsfc &= ~HSFC_FCYCLE; /* clear operation */
|
||
|
hsfc |= HSFC_FCYCLE; /* set erase operation */
|
||
|
hsfc |= HSFC_FGO; /* start */
|
||
|
writew_(hsfc, &cntlr.pch_spi->hsfc);
|
||
|
if (pch_hwseq_wait_for_cycle_complete(timeout, len)) {
|
||
|
printk(BIOS_ERR, "SF: Erase failed at %x\n",
|
||
|
offset - erase_size);
|
||
|
ret = -1;
|
||
|
goto out;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n",
|
||
|
len, start);
|
||
|
|
||
|
out:
|
||
|
spi_release_bus(flash->spi);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static void pch_read_data(uint8_t *data, int len)
|
||
|
{
|
||
|
int i;
|
||
|
uint32_t temp32 = 0;
|
||
|
|
||
|
for (i = 0; i < len; i++) {
|
||
|
if ((i % 4) == 0)
|
||
|
temp32 = readl_(cntlr.data + i);
|
||
|
|
||
|
data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static int pch_hwseq_read(struct spi_flash *flash,
|
||
|
u32 addr, size_t len, void *buf)
|
||
|
{
|
||
|
uint16_t hsfc;
|
||
|
uint16_t timeout = 100 * 60;
|
||
|
uint8_t block_len;
|
||
|
|
||
|
if (addr + len > spi_get_flash_size()) {
|
||
|
printk(BIOS_ERR,
|
||
|
"Attempt to read %x-%x which is out of chip\n",
|
||
|
(unsigned) addr,
|
||
|
(unsigned) addr+(unsigned) len);
|
||
|
return -1;
|
||
|
}
|
||
|
|
||
|
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
|
||
|
writew_(readw_(&cntlr.pch_spi->hsfs), &cntlr.pch_spi->hsfs);
|
||
|
|
||
|
while (len > 0) {
|
||
|
block_len = min(len, cntlr.databytes);
|
||
|
if (block_len > (~addr & 0xff))
|
||
|
block_len = (~addr & 0xff) + 1;
|
||
|
pch_hwseq_set_addr(addr);
|
||
|
hsfc = readw_(&cntlr.pch_spi->hsfc);
|
||
|
hsfc &= ~HSFC_FCYCLE; /* set read operation */
|
||
|
hsfc &= ~HSFC_FDBC; /* clear byte count */
|
||
|
/* set byte count */
|
||
|
hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
|
||
|
hsfc |= HSFC_FGO; /* start */
|
||
|
writew_(hsfc, &cntlr.pch_spi->hsfc);
|
||
|
|
||
|
if (pch_hwseq_wait_for_cycle_complete(timeout, block_len))
|
||
|
return 1;
|
||
|
pch_read_data(buf, block_len);
|
||
|
addr += block_len;
|
||
|
buf += block_len;
|
||
|
len -= block_len;
|
||
|
}
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
/* Fill len bytes from the data array into the fdata/spid registers.
|
||
|
*
|
||
|
* Note that using len > flash->pgm->spi.max_data_write will trash the registers
|
||
|
* following the data registers.
|
||
|
*/
|
||
|
static void pch_fill_data(const uint8_t *data, int len)
|
||
|
{
|
||
|
uint32_t temp32 = 0;
|
||
|
int i;
|
||
|
|
||
|
if (len <= 0)
|
||
|
return;
|
||
|
|
||
|
for (i = 0; i < len; i++) {
|
||
|
if ((i % 4) == 0)
|
||
|
temp32 = 0;
|
||
|
|
||
|
temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
|
||
|
|
||
|
if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
|
||
|
writel_(temp32, cntlr.data + (i - (i % 4)));
|
||
|
}
|
||
|
i--;
|
||
|
if ((i % 4) != 3) /* Write remaining data to regs. */
|
||
|
writel_(temp32, cntlr.data + (i - (i % 4)));
|
||
|
}
|
||
|
|
||
|
static int pch_hwseq_write(struct spi_flash *flash,
|
||
|
u32 addr, size_t len, const void *buf)
|
||
|
{
|
||
|
uint16_t hsfc;
|
||
|
uint16_t timeout = 100 * 60;
|
||
|
uint8_t block_len;
|
||
|
uint32_t start = addr;
|
||
|
|
||
|
if (addr + len > spi_get_flash_size()) {
|
||
|
printk(BIOS_ERR,
|
||
|
"Attempt to write 0x%x-0x%x which is out of chip\n",
|
||
|
(unsigned)addr, (unsigned) (addr+len));
|
||
|
return -1;
|
||
|
}
|
||
|
|
||
|
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
|
||
|
writew_(readw_(&cntlr.pch_spi->hsfs), &cntlr.pch_spi->hsfs);
|
||
|
|
||
|
while (len > 0) {
|
||
|
block_len = min(len, cntlr.databytes);
|
||
|
if (block_len > (~addr & 0xff))
|
||
|
block_len = (~addr & 0xff) + 1;
|
||
|
|
||
|
pch_hwseq_set_addr(addr);
|
||
|
|
||
|
pch_fill_data(buf, block_len);
|
||
|
hsfc = readw_(&cntlr.pch_spi->hsfc);
|
||
|
hsfc &= ~HSFC_FCYCLE; /* clear operation */
|
||
|
hsfc |= HSFC_FCYCLE_WR; /* set write operation */
|
||
|
hsfc &= ~HSFC_FDBC; /* clear byte count */
|
||
|
/* set byte count */
|
||
|
hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
|
||
|
hsfc |= HSFC_FGO; /* start */
|
||
|
writew_(hsfc, &cntlr.pch_spi->hsfc);
|
||
|
|
||
|
if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) {
|
||
|
printk(BIOS_ERR, "SF: write failure at %x\n", addr);
|
||
|
return -1;
|
||
|
}
|
||
|
addr += block_len;
|
||
|
buf += block_len;
|
||
|
len -= block_len;
|
||
|
}
|
||
|
printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
|
||
|
(unsigned) (addr - start), start);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
|
||
|
static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi)
|
||
|
{
|
||
|
struct spi_flash *flash = NULL;
|
||
|
u32 berase;
|
||
|
|
||
|
flash = malloc(sizeof(*flash));
|
||
|
if (!flash) {
|
||
|
printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
|
||
|
return NULL;
|
||
|
}
|
||
|
|
||
|
flash->spi = spi;
|
||
|
flash->name = "Opaque HW-sequencing";
|
||
|
|
||
|
flash->write = pch_hwseq_write;
|
||
|
flash->erase = pch_hwseq_erase;
|
||
|
flash->read = pch_hwseq_read;
|
||
|
pch_hwseq_set_addr(0);
|
||
|
|
||
|
berase = (cntlr.hsfs >> SPIBAR_HSFS_BERASE_OFFSET) &
|
||
|
SPIBAR_HSFS_BERASE_MASK;
|
||
|
|
||
|
switch (berase) {
|
||
|
case 0:
|
||
|
flash->sector_size = 256;
|
||
|
break;
|
||
|
case 1:
|
||
|
flash->sector_size = 4096;
|
||
|
break;
|
||
|
case 2:
|
||
|
flash->sector_size = 8192;
|
||
|
break;
|
||
|
case 3:
|
||
|
flash->sector_size = 65536;
|
||
|
break;
|
||
|
}
|
||
|
|
||
|
flash->size = spi_get_flash_size();
|
||
|
|
||
|
return flash;
|
||
|
}
|