97 lines
3.3 KiB
C
97 lines
3.3 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* The L2 cache definitions here only apply to SECC/SECC2 P6 family CPUs
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* with Klamath (63x), Deschutes (65x) and Katmai (67x) cores.
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* It is not required for Coppermine (68x) and Tualatin (6bx) cores.
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* It is currently not known if Celerons with Mendocino core require
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* the special initialization.
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* Covington-core Celerons do not have L2 cache.
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*/
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/* This is a straight port from coreboot v1. */
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#ifndef __P6_L2_CACHE_H
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#define __P6_L2_CACHE_H
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#define IA32_PLATFORM_ID 0x17
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#define EBL_CR_POWERON 0x2A
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#define BBL_CR_D0 0x88
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#define BBL_CR_D1 0x89
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#define BBL_CR_D2 0x8A
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#define BBL_CR_D3 0x8B
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#define BBL_CR_ADDR 0x116
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#define BBL_CR_DECC 0x118
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#define BBL_CR_CTL 0x119
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#define BBL_CR_TRIG 0x11A
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#define BBL_CR_BUSY 0x11B
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#define BBL_CR_CTL3 0x11E
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#define BBLCR3_L2_CONFIGURED (1<<0)
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/* bits [4:1] */
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#define BBLCR3_L2_LATENCY 0x1e
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#define BBLCR3_L2_ECC_CHECK_ENABLE (1<<5)
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#define BBLCR3_L2_ADDR_PARITY_ENABLE (1<<6)
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#define BBLCR3_L2_CRTN_PARITY_ENABLE (1<<7)
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#define BBLCR3_L2_ENABLED (1<<8)
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/* bits [17:13] */
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#define BBLCR3_L2_SIZE (0x1f << 13)
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#define BBLCR3_L2_SIZE_256K (0x01 << 13)
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#define BBLCR3_L2_SIZE_512K (0x02 << 13)
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#define BBLCR3_L2_SIZE_1M (0x04 << 13)
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#define BBLCR3_L2_SIZE_2M (0x08 << 13)
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#define BBLCR3_L2_SIZE_4M (0x10 << 13)
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/* bits [22:20] */
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#define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20);
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/* TODO: This bitmask does not agree with Intel's documentation.
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* Get confirmation one way or another.
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*/
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#define BBLCR3_L2_SUPPLIED_ECC 0x40000
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#define BBLCR3_L2_HARDWARE_DISABLE (1<<23)
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/* Also known as... */
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#define BBLCR3_L2_NOT_PRESENT (1<<23)
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/* L2 commands */
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#define L2CMD_RLU 0x0c /* 01100 Data read w/ LRU update */
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#define L2CMD_TRR 0x0e /* 01110 Tag read with data read */
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#define L2CMD_TI 0x0f /* 01111 Tag inquiry */
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#define L2CMD_CR 0x02 /* 00010 L2 control register read */
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#define L2CMD_CW 0x03 /* 00011 L2 control register write */
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#define L2CMD_TWR 0x08 /* 010-- Tag read w/ data read */
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#define L2CMD_TWW 0x1c /* 111-- Tag write w/ data write */
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#define L2CMD_TW 0x10 /* 100-- Tag write */
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/* MESI encode for L2 commands above */
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#define L2CMD_MESI_M 3
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#define L2CMD_MESI_E 2
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#define L2CMD_MESI_S 1
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#define L2CMD_MESI_I 0
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extern int calculate_l2_latency(void);
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extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command);
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extern int read_l2(u32 address);
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extern int write_l2(u32 address, u32 data);
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extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low);
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extern int calculate_l2_cache_size(void);
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extern int calculate_l2_physical_address_range(void);
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extern int set_l2_ecc(void);
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extern int p6_configure_l2_cache(void);
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#endif /* __P6_L2_CACHE_H */
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