148 lines
6.1 KiB
Markdown
148 lines
6.1 KiB
Markdown
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# Dell OptiPlex 9010
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This page describes how to run coreboot on Dell OptiPlex 9010 SFF.
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![](optiplex_9010.jpg)
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## Technology
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```eval_rst
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+------------+---------------------------------------------------------------+
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| CPU | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge) |
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+------------+---------------------------------------------------------------+
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| DRAM | Up to 4 DIMM slots, up to 32GB 1600MHz non-ECC DDR3 SDRAM |
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+------------+---------------------------------------------------------------+
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| Chipset | Intel Q77 Express |
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+------------+---------------------------------------------------------------+
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| Super I/O | SMSC SCH5545 (or SCH5544) with Environmental Controller |
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+------------+---------------------------------------------------------------+
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| TPM | ST Microelectronics ST33ZP24 |
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+------------+---------------------------------------------------------------+
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| Boot | From USB, SATA, NVMe (using PCIe x4 expansion card) |
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+------------+---------------------------------------------------------------+
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| Power | 200W-275W PSU |
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+------------+---------------------------------------------------------------+
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```
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More specifications on [Dell OptiPlex 9010 specifications].
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## Required proprietary blobs
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```eval_rst
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+------------------+---------------------------------+---------------------+
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| Binary file | Apply | Required / Optional |
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+==================+=================================+=====================+
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| smsc_sch5545.bin | SMSC SCH5545 EC | Optional |
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+------------------+---------------------------------+---------------------+
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| microcode | CPU microcode | Required |
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+------------------+---------------------------------+---------------------+
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```
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Microcode updates are automatically included into the coreboot image by build
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system from the `3rdparty/intel-microcode` submodule.
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SMSC SC5545 EC firmware is optional, however lack of the binary will result in
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EC malfunction after power failure and fans running at full speed. The blob can
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be extracted from original firmware. It should be located under a file with
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GUID D386BEB8-4B54-4E69-94F5-06091F67E0D3, raw section. The file begins with a
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signature `SMSCUBIM`. The easiest way to do this is to use [UEFITool] and
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`Extract body` option on the raw section of the file.
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## Flashing coreboot
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```eval_rst
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+---------------------+--------------------------+
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| Type | Value |
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+=====================+==========================+
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| Socketed flash | no |
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+---------------------+--------------------------+
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| Model | MX25L6406E/MX25L3206E |
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+---------------------+--------------------------+
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| Size | 8 + 4 MiB |
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+---------------------+--------------------------+
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| Package | SOIC-16 + SOIC-8 |
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+---------------------+--------------------------+
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| Write protection | chipset PRR |
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+---------------------+--------------------------+
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| Dual BIOS feature | no |
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+---------------------+--------------------------+
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| Internal flashing | yes |
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+---------------------+--------------------------+
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```
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### Internal programming
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The SPI flash can be accessed using [flashrom].
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flashrom -p internal -w coreboot.rom --ifd -i bios
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Internal programming will not work when migrating from original UEFI firmware.
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One will have to short the SERVICE_MODE jumper to enable HMRFPO and then boot
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the machine to flash it.
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### External programming
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The external access to flash chip is available through standard SOP-8 clip
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and/or SOP-16 clip on the right side of the CPU fan (marked on the board
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image). The voltage of SPI flash is 3.3V.
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There are no restrictions as to the programmer device. It is only recommended
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to flash firmware without supplying power. There are no diodes connected to the
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flash chips. External programming can be performed, for example using OrangePi
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and Armbian. You can use linux_spi driver which provides communication with SPI
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devices. Example command to program SPI flash with OrangePi using linux_spi:
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flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000
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## Schematics
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There are no schematics for SFF, but if one looks for MT/DT schematics, they
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can be found publicly. Most of the schematics should match the SFF (although
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MT/DT has additional PCIe and PCI slot).
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## Known issues
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- There seems to be a problem with DRAM clearing on reboot. The SSKPD register
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still contains 0xCAFE which leads to reset loop.
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## Untested
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Not all mainboard's peripherals and functions were tested because of lack of
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the cables or not being populated on the board case.
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- Internal USB 2.0 header
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- Wake from S3 using serial port
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- Wake-on-Lan from ACPI S4/S5
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## Working
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- USB 3.0 and 2.0 rear and front ports (SeaBIOS and Linux 4.19)
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- Gigabit Ethernet
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- VGA and 2x DP port using libgfxinit
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- flashrom
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- PCIe x1 WiFi in PCIe x4 slot
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- NVMe PCIe x4 using PCIe x4 expansion card
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- PCIe x16 PEG port using Dell Radeon HD 7570
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- SATA ports (SATA disks and DVD)
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- Super I/O serial port 0 (RS232 DB9 connector on the rear side)
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- SMBus (reading SPD from DIMMs)
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- CPU initialization using Intel i7-3770
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- Sandy Bridge/Ivy Bridge native RAM initialization
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- SeaBIOS payload (version rel-1.13.0)
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- PS/2 keyboard and mouse (including wake support)
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- LPC debug header (requires soldering of the pin header and shorting RF24 for
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LPC clock)
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- USB debug dongle (the most bottom USB 2.0 port under RJ45 on the read side)
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- SMSC SCH5545 Super I/O initialization
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- SMSC SCH5545 EC initialization and firmware update
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- SMSC SCH5545 EC automatic fan control
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- TPM 1.2
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- Booting Debian 10, Ubuntu 18.04, QubesOS R4.01
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- Boot with cleaned ME
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- Intruder detection
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- Wake-on-Lan from ACPI S3
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[flashrom]: https://flashrom.org/Flashrom
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[Dell OptiPlex 9010 specifications]: https://www.dell.com/downloads/global/products/optix/en/dell_optiplex_9010_spec_sheet.pdf
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[UEFITool]: https://github.com/LongSoft/UEFITool
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