2012-12-27 23:15:51 +01:00
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/*
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2013-04-05 22:42:39 +02:00
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* This file is part of the coreboot project.
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2012-12-27 23:15:51 +01:00
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*
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2014-04-08 03:45:14 +02:00
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* Copyright (C) 2014 Google, Inc.
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2012-12-27 23:15:51 +01:00
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*
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2013-04-05 22:42:39 +02:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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2012-12-27 23:15:51 +01:00
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2013-04-05 22:42:39 +02:00
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#ifndef _DEVICE_I2C_H_
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#define _DEVICE_I2C_H_
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2012-12-27 23:15:51 +01:00
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2013-06-30 12:47:33 +02:00
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#include <stdint.h>
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2014-04-08 03:45:14 +02:00
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#include <stdlib.h>
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2013-06-30 12:47:33 +02:00
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acpi_device: Add support for writing ACPI I2C descriptors
Add required definitions to describe an ACPI I2C bus and a method to
write the I2cSerialBus() descriptor to the SSDT.
This will be used by device drivers to describe their I2C resources to
the OS. The devicetree i2c device can supply the address and 7 or 10
bit mode as well as indicate the GPIO controller device, and the bus
speed can be fixed or configured by the driver.
chip.h:
struct drivers_i2c_generic_config {
enum i2c_speed bus_speed;
};
generic.c:
void acpi_fill_ssdt_generator(struct device *dev) {
struct drivers_i2c_generic_config *config = dev->chip_info;
struct acpi_i2c i2c = {
.address = dev->path->i2c.device,
.mode_10bit = dev->path.i2c.mode_10bit,
.speed = config->bus_speed ? : I2C_SPEED_FAST,
.resource = acpi_device_path(dev->bus->dev)
};
...
acpi_device_write_i2c(&i2c);
...
}
devicetree.cb:
device pci 15.0 on
chip drivers/i2c/generic
device i2c 10.0 on end
end
end
SSDT.dsl:
I2cSerialBus (0x10, ControllerInitiated, 400000, AddressingMode7Bit,
"\\_SB.PCI0.I2C0", 0, ResourceConsumer)
Change-Id: I598401ac81a92c72f19da0271af1e218580a6c49
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14935
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-10 05:10:47 +02:00
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enum i2c_speed {
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I2C_SPEED_STANDARD = 100000,
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I2C_SPEED_FAST = 400000,
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I2C_SPEED_FAST_PLUS = 1000000,
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I2C_SPEED_HIGH = 3400000,
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I2C_SPEED_FAST_ULTRA = 5000000,
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};
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enum i2c_address_mode {
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I2C_MODE_7_BIT,
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I2C_MODE_10_BIT
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};
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2014-04-08 03:45:14 +02:00
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struct i2c_seg
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{
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int read;
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uint8_t chip;
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uint8_t *buf;
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int len;
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};
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2017-03-07 03:01:04 +01:00
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int platform_i2c_transfer(unsigned int bus, struct i2c_seg *segments,
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int count);
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2014-05-06 03:03:46 +02:00
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#define SOFTWARE_I2C_MAX_BUS 10 /* increase as necessary */
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struct software_i2c_ops {
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2017-03-07 03:01:04 +01:00
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void (*set_sda)(unsigned int bus, int high);
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void (*set_scl)(unsigned int bus, int high);
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int (*get_sda)(unsigned int bus);
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int (*get_scl)(unsigned int bus);
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2014-05-06 03:03:46 +02:00
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};
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extern struct software_i2c_ops *software_i2c[];
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2017-03-07 03:01:04 +01:00
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int software_i2c_transfer(unsigned int bus, struct i2c_seg *segments,
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int count);
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void software_i2c_wedge_ack(unsigned int bus, u8 chip);
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void software_i2c_wedge_read(unsigned int bus, u8 chip, u8 reg, int bit_count);
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void software_i2c_wedge_write(unsigned int bus, u8 chip, u8 reg, int bit_count);
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2014-05-06 03:03:46 +02:00
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2017-03-07 03:01:04 +01:00
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int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t *data,
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2016-03-15 07:38:44 +01:00
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uint8_t mask, uint8_t shift);
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2017-03-07 03:01:04 +01:00
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int i2c_write_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t data,
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2016-03-15 07:38:44 +01:00
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uint8_t mask, uint8_t shift);
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2014-05-06 03:03:46 +02:00
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/*
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* software_i2c is supposed to be a debug feature. It's usually not compiled in,
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* but when it is it can be dynamically enabled at runtime for certain busses.
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* Need this ugly stub to arbitrate since I2C device drivers hardcode
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* 'i2c_transfer()' as their entry point.
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*/
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2017-03-07 03:01:04 +01:00
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static inline int i2c_transfer(unsigned int bus, struct i2c_seg *segments,
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2014-05-06 03:03:46 +02:00
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int count)
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{
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if (CONFIG_SOFTWARE_I2C)
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if (bus < SOFTWARE_I2C_MAX_BUS && software_i2c[bus])
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return software_i2c_transfer(bus, segments, count);
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return platform_i2c_transfer(bus, segments, count);
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}
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2014-04-08 03:45:14 +02:00
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/*
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* Read a raw chunk of data in one segment and one frame.
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*
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* [start][slave addr][r][data][stop]
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*/
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2017-03-07 03:01:04 +01:00
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static inline int i2c_read_raw(unsigned int bus, uint8_t chip, uint8_t *data,
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2014-04-08 03:45:14 +02:00
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int len)
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{
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struct i2c_seg seg =
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{ .read = 1, .chip = chip, .buf = data, .len = len };
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return i2c_transfer(bus, &seg, 1);
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}
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/*
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* Write a raw chunk of data in one segment and one frame.
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*
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* [start][slave addr][w][data][stop]
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*/
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2017-03-07 03:01:04 +01:00
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static inline int i2c_write_raw(unsigned int bus, uint8_t chip, uint8_t *data,
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2017-03-07 21:18:53 +01:00
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int len)
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2014-04-08 03:45:14 +02:00
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{
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struct i2c_seg seg =
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{ .read = 0, .chip = chip, .buf = data, .len = len };
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return i2c_transfer(bus, &seg, 1);
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}
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2016-02-01 10:33:49 +01:00
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/**
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* Read multi-bytes with two segments in one frame
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*
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* [start][slave addr][w][register addr][start][slave addr][r][data...][stop]
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*/
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2017-03-07 03:01:04 +01:00
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static inline int i2c_read_bytes(unsigned int bus, uint8_t chip, uint8_t reg,
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2016-02-01 10:33:49 +01:00
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uint8_t *data, int len)
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{
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struct i2c_seg seg[2];
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seg[0].read = 0;
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seg[0].chip = chip;
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seg[0].buf = ®
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seg[0].len = 1;
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seg[1].read = 1;
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seg[1].chip = chip;
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seg[1].buf = data;
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seg[1].len = len;
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return i2c_transfer(bus, seg, ARRAY_SIZE(seg));
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}
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2014-04-08 03:45:14 +02:00
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/**
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* Read a byte with two segments in one frame
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*
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* [start][slave addr][w][register addr][start][slave addr][r][data][stop]
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*/
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2017-03-07 03:01:04 +01:00
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static inline int i2c_readb(unsigned int bus, uint8_t chip, uint8_t reg,
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2014-04-08 03:45:14 +02:00
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uint8_t *data)
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{
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struct i2c_seg seg[2];
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seg[0].read = 0;
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seg[0].chip = chip;
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seg[0].buf = ®
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seg[0].len = 1;
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seg[1].read = 1;
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seg[1].chip = chip;
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seg[1].buf = data;
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seg[1].len = 1;
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return i2c_transfer(bus, seg, ARRAY_SIZE(seg));
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}
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/**
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* Write a byte with one segment in one frame.
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*
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* [start][slave addr][w][register addr][data][stop]
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*/
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2017-03-07 03:01:04 +01:00
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static inline int i2c_writeb(unsigned int bus, uint8_t chip, uint8_t reg,
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2014-04-08 03:45:14 +02:00
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uint8_t data)
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{
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struct i2c_seg seg;
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uint8_t buf[] = {reg, data};
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seg.read = 0;
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seg.chip = chip;
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seg.buf = buf;
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seg.len = ARRAY_SIZE(buf);
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return i2c_transfer(bus, &seg, 1);
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}
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2012-12-27 23:15:51 +01:00
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2016-06-08 00:38:14 +02:00
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/* I2C bus operation for ramstage drivers */
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struct device;
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struct i2c_bus_operations {
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/*
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* This is an SOC specific method that can be provided to translate the
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* 'struct device' for an I2C controller into a unique I2C bus number.
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* Returns -1 if the bus number for this device cannot be determined.
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*/
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int (*dev_to_bus)(struct device *dev);
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};
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/* Return I2C bus number for provided device, -1 if not found */
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int i2c_dev_find_bus(struct device *dev);
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/* Variants of I2C helper functions that take a device instead of bus number */
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int i2c_dev_transfer(struct device *dev, struct i2c_seg *segments, int count);
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int i2c_dev_readb(struct device *dev, uint8_t reg, uint8_t *data);
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int i2c_dev_writeb(struct device *dev, uint8_t reg, uint8_t data);
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int i2c_dev_read_bytes(struct device *dev, uint8_t reg, uint8_t *data, int len);
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int i2c_dev_read_raw(struct device *dev, uint8_t *data, int len);
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int i2c_dev_write_raw(struct device *dev, uint8_t *data, int len);
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2013-04-05 22:42:39 +02:00
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#endif /* _DEVICE_I2C_H_ */
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