2016-06-07 22:40:11 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2009 Vipin Kumar, ST Microelectronics
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
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#include <arch/acpigen.h>
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2016-06-07 22:40:11 +02:00
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#include <arch/io.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/i2c.h>
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2016-06-21 19:41:19 +02:00
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#include <string.h>
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2016-06-07 22:40:11 +02:00
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#include <timer.h>
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#include "lpss_i2c.h"
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struct lpss_i2c_regs {
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uint32_t control;
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uint32_t target_addr;
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uint32_t slave_addr;
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uint32_t master_addr;
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uint32_t cmd_data;
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uint32_t ss_scl_hcnt;
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uint32_t ss_scl_lcnt;
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uint32_t fs_scl_hcnt;
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uint32_t fs_scl_lcnt;
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uint32_t hs_scl_hcnt;
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uint32_t hs_scl_lcnt;
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uint32_t intr_stat;
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uint32_t intr_mask;
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uint32_t raw_intr_stat;
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uint32_t rx_thresh;
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uint32_t tx_thresh;
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uint32_t clear_intr;
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uint32_t clear_rx_under_intr;
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uint32_t clear_rx_over_intr;
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uint32_t clear_tx_over_intr;
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uint32_t clear_rd_req_intr;
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uint32_t clear_tx_abrt_intr;
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uint32_t clear_rx_done_intr;
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uint32_t clear_activity_intr;
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uint32_t clear_stop_det_intr;
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uint32_t clear_start_det_intr;
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uint32_t clear_gen_call_intr;
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uint32_t enable;
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uint32_t status;
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uint32_t tx_level;
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uint32_t rx_level;
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uint32_t sda_hold;
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uint32_t tx_abort_source;
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2016-09-12 20:20:27 +02:00
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uint32_t slv_data_nak_only;
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uint32_t dma_cr;
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uint32_t dma_tdlr;
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uint32_t dma_rdlr;
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uint32_t sda_setup;
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uint32_t ack_general_call;
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uint32_t enable_status;
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uint32_t fs_spklen;
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uint32_t hs_spklen;
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uint32_t clr_restart_det;
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uint32_t comp_param1;
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uint32_t comp_version;
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uint32_t comp_type;
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2016-06-07 22:40:11 +02:00
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} __attribute__((packed));
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2016-09-01 23:22:34 +02:00
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/* Use a ~4ms timeout for various operations */
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#define LPSS_I2C_TIMEOUT_US 4000
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2016-06-07 22:40:11 +02:00
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/* High and low times in different speed modes (in ns) */
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enum {
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lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
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/* SDA Hold Time */
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DEFAULT_SDA_HOLD_TIME = 300,
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2016-06-07 22:40:11 +02:00
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/* Standard Speed */
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MIN_SS_SCL_HIGHTIME = 4000,
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MIN_SS_SCL_LOWTIME = 4700,
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lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
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/* Fast Speed */
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2016-06-07 22:40:11 +02:00
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MIN_FS_SCL_HIGHTIME = 600,
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MIN_FS_SCL_LOWTIME = 1300,
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lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
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/* Fast Plus Speed */
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MIN_FP_SCL_HIGHTIME = 260,
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MIN_FP_SCL_LOWTIME = 500,
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2016-06-07 22:40:11 +02:00
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/* High Speed */
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MIN_HS_SCL_HIGHTIME = 60,
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MIN_HS_SCL_LOWTIME = 160,
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};
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/* Control register definitions */
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enum {
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CONTROL_MASTER_MODE = (1 << 0),
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CONTROL_SPEED_SS = (1 << 1),
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CONTROL_SPEED_FS = (1 << 2),
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CONTROL_SPEED_HS = (3 << 1),
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CONTROL_SPEED_MASK = (3 << 1),
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CONTROL_10BIT_SLAVE = (1 << 3),
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CONTROL_10BIT_MASTER = (1 << 4),
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CONTROL_RESTART_ENABLE = (1 << 5),
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CONTROL_SLAVE_DISABLE = (1 << 6),
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};
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/* Command/Data register definitions */
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enum {
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CMD_DATA_CMD = (1 << 8),
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CMD_DATA_STOP = (1 << 9),
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};
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/* Status register definitions */
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enum {
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STATUS_ACTIVITY = (1 << 0),
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STATUS_TX_FIFO_NOT_FULL = (1 << 1),
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STATUS_TX_FIFO_EMPTY = (1 << 2),
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STATUS_RX_FIFO_NOT_EMPTY = (1 << 3),
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STATUS_RX_FIFO_FULL = (1 << 4),
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STATUS_MASTER_ACTIVITY = (1 << 5),
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STATUS_SLAVE_ACTIVITY = (1 << 6),
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};
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/* Enable register definitions */
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enum {
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ENABLE_CONTROLLER = (1 << 0),
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};
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/* Interrupt status register definitions */
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enum {
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INTR_STAT_RX_UNDER = (1 << 0),
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INTR_STAT_RX_OVER = (1 << 1),
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INTR_STAT_RX_FULL = (1 << 2),
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INTR_STAT_TX_OVER = (1 << 3),
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INTR_STAT_TX_EMPTY = (1 << 4),
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INTR_STAT_RD_REQ = (1 << 5),
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INTR_STAT_TX_ABORT = (1 << 6),
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INTR_STAT_RX_DONE = (1 << 7),
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INTR_STAT_ACTIVITY = (1 << 8),
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INTR_STAT_STOP_DET = (1 << 9),
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INTR_STAT_START_DET = (1 << 10),
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INTR_STAT_GEN_CALL = (1 << 11),
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};
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/* Enable this I2C controller */
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static void lpss_i2c_enable(struct lpss_i2c_regs *regs)
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{
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uint32_t enable = read32(®s->enable);
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if (!(enable & ENABLE_CONTROLLER))
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write32(®s->enable, enable | ENABLE_CONTROLLER);
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}
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/* Disable this I2C controller */
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static int lpss_i2c_disable(struct lpss_i2c_regs *regs)
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{
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uint32_t enable = read32(®s->enable);
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if (enable & ENABLE_CONTROLLER) {
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struct stopwatch sw;
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write32(®s->enable, enable & ~ENABLE_CONTROLLER);
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/* Wait for enable bit to clear */
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stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US);
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2016-09-12 20:20:27 +02:00
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while (read32(®s->enable_status) & ENABLE_CONTROLLER)
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2016-06-07 22:40:11 +02:00
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if (stopwatch_expired(&sw))
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return -1;
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}
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return 0;
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}
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/* Wait for this I2C controller to go idle for transmit */
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static int lpss_i2c_wait_for_bus_idle(struct lpss_i2c_regs *regs)
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{
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struct stopwatch sw;
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/* Start timeout for up to 16 bytes in FIFO */
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stopwatch_init_usecs_expire(&sw, 16 * LPSS_I2C_TIMEOUT_US);
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while (!stopwatch_expired(&sw)) {
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uint32_t status = read32(®s->status);
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/* Check for master activity and keep waiting */
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if (status & STATUS_MASTER_ACTIVITY)
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continue;
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/* Check for TX FIFO empty to indicate TX idle */
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if (status & STATUS_TX_FIFO_EMPTY)
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return 0;
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}
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/* Timed out while waiting for bus to go idle */
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return -1;
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}
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/* Transfer one byte of one segment, sending stop bit if requested */
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static int lpss_i2c_transfer_byte(struct lpss_i2c_regs *regs,
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struct i2c_seg *segment,
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size_t byte, int send_stop)
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{
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struct stopwatch sw;
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uint32_t cmd = CMD_DATA_CMD; /* Read op */
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stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US);
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if (!segment->read) {
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/* Write op only: Wait for FIFO not full */
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while (!(read32(®s->status) & STATUS_TX_FIFO_NOT_FULL)) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR, "I2C transmit timeout\n");
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return -1;
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}
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}
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cmd = segment->buf[byte];
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}
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/* Send stop on last byte, if desired */
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if (send_stop && byte == segment->len - 1)
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cmd |= CMD_DATA_STOP;
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write32(®s->cmd_data, cmd);
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if (segment->read) {
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/* Read op only: Wait for FIFO data and store it */
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while (!(read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY)) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR, "I2C receive timeout\n");
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return -1;
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}
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}
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segment->buf[byte] = read32(®s->cmd_data);
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}
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return 0;
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}
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/* Global I2C bus handler, defined in include/i2c.h */
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int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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{
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struct stopwatch sw;
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struct lpss_i2c_regs *regs;
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size_t byte;
|
2016-09-12 20:20:27 +02:00
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|
int ret = -1;
|
2016-06-07 22:40:11 +02:00
|
|
|
|
|
|
|
if (count <= 0 || !segments)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus);
|
|
|
|
if (!regs) {
|
|
|
|
printk(BIOS_ERR, "I2C bus %u base address not found\n", bus);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-09-12 20:20:27 +02:00
|
|
|
lpss_i2c_enable(regs);
|
2016-06-07 22:40:11 +02:00
|
|
|
|
|
|
|
if (lpss_i2c_wait_for_bus_idle(regs)) {
|
|
|
|
printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus);
|
2016-09-12 20:20:27 +02:00
|
|
|
goto out;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Process each segment */
|
|
|
|
while (count--) {
|
|
|
|
/* Set target slave address */
|
|
|
|
write32(®s->target_addr, segments->chip);
|
|
|
|
|
|
|
|
/* Read or write each byte in segment */
|
|
|
|
for (byte = 0; byte < segments->len; byte++) {
|
|
|
|
/*
|
|
|
|
* Set stop condition on final segment only.
|
|
|
|
* Repeated start will be automatically generated
|
|
|
|
* by the controller on R->W or W->R switch.
|
|
|
|
*/
|
|
|
|
if (lpss_i2c_transfer_byte(regs, segments, byte,
|
|
|
|
count == 0) < 0) {
|
|
|
|
printk(BIOS_ERR, "I2C %s failed: bus %u "
|
|
|
|
"addr 0x%02x\n", segments->read ?
|
|
|
|
"read" : "write", bus, segments->chip);
|
2016-09-12 20:20:27 +02:00
|
|
|
goto out;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
segments++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait for interrupt status to indicate transfer is complete */
|
|
|
|
stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US);
|
|
|
|
while (!(read32(®s->raw_intr_stat) & INTR_STAT_STOP_DET)) {
|
|
|
|
if (stopwatch_expired(&sw)) {
|
|
|
|
printk(BIOS_ERR, "I2C stop bit not received\n");
|
2016-09-12 20:20:27 +02:00
|
|
|
goto out;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read to clear INTR_STAT_STOP_DET */
|
|
|
|
read32(®s->clear_stop_det_intr);
|
|
|
|
|
|
|
|
/* Wait for the bus to go idle */
|
|
|
|
if (lpss_i2c_wait_for_bus_idle(regs)) {
|
|
|
|
printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus);
|
2016-09-12 20:20:27 +02:00
|
|
|
goto out;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Flush the RX FIFO in case it is not empty */
|
|
|
|
stopwatch_init_usecs_expire(&sw, 16 * LPSS_I2C_TIMEOUT_US);
|
|
|
|
while (read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY) {
|
|
|
|
if (stopwatch_expired(&sw)) {
|
|
|
|
printk(BIOS_ERR, "I2C timeout flushing RX FIFO\n");
|
2016-09-12 20:20:27 +02:00
|
|
|
goto out;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
read32(®s->cmd_data);
|
|
|
|
}
|
|
|
|
|
2016-09-12 20:20:27 +02:00
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
out:
|
|
|
|
read32(®s->clear_intr);
|
|
|
|
lpss_i2c_disable(regs);
|
|
|
|
return ret;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
|
2016-06-21 19:41:19 +02:00
|
|
|
/*
|
|
|
|
* Write ACPI object to describe speed configuration.
|
|
|
|
*
|
|
|
|
* ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
|
|
|
|
*
|
|
|
|
* SSCN: I2C_SPEED_STANDARD
|
|
|
|
* FMCN: I2C_SPEED_FAST
|
|
|
|
* FPCN: I2C_SPEED_FAST_PLUS
|
|
|
|
* HSCN: I2C_SPEED_HIGH
|
|
|
|
*/
|
|
|
|
static void lpss_i2c_acpi_write_speed_config(
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
const struct lpss_i2c_speed_config *config)
|
2016-06-07 22:40:11 +02:00
|
|
|
{
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
if (!config)
|
|
|
|
return;
|
|
|
|
if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (config->speed >= I2C_SPEED_HIGH)
|
|
|
|
acpigen_write_name("HSCN");
|
|
|
|
else if (config->speed >= I2C_SPEED_FAST_PLUS)
|
|
|
|
acpigen_write_name("FPCN");
|
|
|
|
else if (config->speed >= I2C_SPEED_FAST)
|
|
|
|
acpigen_write_name("FMCN");
|
|
|
|
else
|
|
|
|
acpigen_write_name("SSCN");
|
|
|
|
|
|
|
|
/* Package () { scl_lcnt, scl_hcnt, sda_hold } */
|
|
|
|
acpigen_write_package(3);
|
|
|
|
acpigen_write_word(config->scl_hcnt);
|
|
|
|
acpigen_write_word(config->scl_lcnt);
|
|
|
|
acpigen_write_dword(config->sda_hold);
|
|
|
|
acpigen_pop_len();
|
|
|
|
}
|
|
|
|
|
2016-06-21 19:41:19 +02:00
|
|
|
void lpss_i2c_acpi_fill_ssdt(const struct lpss_i2c_speed_config *override)
|
|
|
|
{
|
|
|
|
const struct lpss_i2c_speed_config *sptr;
|
|
|
|
struct lpss_i2c_speed_config sgen;
|
|
|
|
enum i2c_speed speeds[LPSS_I2C_SPEED_CONFIG_COUNT] = {
|
|
|
|
I2C_SPEED_STANDARD,
|
|
|
|
I2C_SPEED_FAST,
|
|
|
|
I2C_SPEED_FAST_PLUS,
|
|
|
|
I2C_SPEED_HIGH,
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Report timing values for the OS driver */
|
|
|
|
for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) {
|
|
|
|
/* Generate speed config for default case */
|
|
|
|
if (lpss_i2c_gen_speed_config(speeds[i], &sgen) < 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Apply board specific override for this speed if found */
|
|
|
|
for (sptr = override; sptr && sptr->speed; sptr++) {
|
|
|
|
if (sptr->speed == speeds[i]) {
|
|
|
|
memcpy(&sgen, sptr, sizeof(sgen));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Generate ACPI based on selected speed config */
|
|
|
|
lpss_i2c_acpi_write_speed_config(&sgen);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
int lpss_i2c_set_speed_config(unsigned bus,
|
|
|
|
const struct lpss_i2c_speed_config *config)
|
|
|
|
{
|
|
|
|
struct lpss_i2c_regs *regs;
|
2016-06-07 22:40:11 +02:00
|
|
|
void *hcnt_reg, *lcnt_reg;
|
|
|
|
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus);
|
|
|
|
if (!regs || !config)
|
|
|
|
return -1;
|
2016-06-07 22:40:11 +02:00
|
|
|
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
/* Nothing to do if no values are set */
|
|
|
|
if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold)
|
|
|
|
return 0;
|
2016-06-07 22:40:11 +02:00
|
|
|
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
if (config->speed >= I2C_SPEED_FAST_PLUS) {
|
|
|
|
/* Fast-Plus and High speed */
|
2016-06-07 22:40:11 +02:00
|
|
|
hcnt_reg = ®s->hs_scl_hcnt;
|
|
|
|
lcnt_reg = ®s->hs_scl_lcnt;
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
} else if (config->speed >= I2C_SPEED_FAST) {
|
|
|
|
/* Fast speed */
|
|
|
|
hcnt_reg = ®s->fs_scl_hcnt;
|
|
|
|
lcnt_reg = ®s->fs_scl_lcnt;
|
|
|
|
} else {
|
|
|
|
/* Standard speed */
|
|
|
|
hcnt_reg = ®s->ss_scl_hcnt;
|
|
|
|
lcnt_reg = ®s->ss_scl_lcnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SCL count must be set after the speed is selected */
|
|
|
|
if (config->scl_hcnt)
|
|
|
|
write32(hcnt_reg, config->scl_hcnt);
|
|
|
|
if (config->scl_lcnt)
|
|
|
|
write32(lcnt_reg, config->scl_lcnt);
|
|
|
|
|
|
|
|
/* Set SDA Hold Time register */
|
|
|
|
if (config->sda_hold)
|
|
|
|
write32(®s->sda_hold, config->sda_hold);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int lpss_i2c_gen_speed_config(enum i2c_speed speed,
|
|
|
|
struct lpss_i2c_speed_config *config)
|
|
|
|
{
|
|
|
|
const int ic_clk = CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ;
|
|
|
|
uint16_t hcnt_min, lcnt_min;
|
|
|
|
|
|
|
|
/* Clock must be provided by Kconfig */
|
|
|
|
if (!ic_clk || !config)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
if (speed >= I2C_SPEED_HIGH) {
|
|
|
|
/* High speed */
|
2016-06-07 22:40:11 +02:00
|
|
|
hcnt_min = MIN_HS_SCL_HIGHTIME;
|
|
|
|
lcnt_min = MIN_HS_SCL_LOWTIME;
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
} else if (speed >= I2C_SPEED_FAST_PLUS) {
|
|
|
|
/* Fast-Plus speed */
|
|
|
|
hcnt_min = MIN_FP_SCL_HIGHTIME;
|
|
|
|
lcnt_min = MIN_FP_SCL_LOWTIME;
|
2016-06-07 22:40:11 +02:00
|
|
|
} else if (speed >= I2C_SPEED_FAST) {
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
/* Fast speed */
|
2016-06-07 22:40:11 +02:00
|
|
|
hcnt_min = MIN_FS_SCL_HIGHTIME;
|
|
|
|
lcnt_min = MIN_FS_SCL_LOWTIME;
|
|
|
|
} else {
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
/* Standard speed */
|
2016-06-07 22:40:11 +02:00
|
|
|
hcnt_min = MIN_SS_SCL_HIGHTIME;
|
|
|
|
lcnt_min = MIN_SS_SCL_LOWTIME;
|
|
|
|
}
|
|
|
|
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
config->speed = speed;
|
|
|
|
config->scl_hcnt = ic_clk * hcnt_min / KHz;
|
|
|
|
config->scl_lcnt = ic_clk * lcnt_min / KHz;
|
|
|
|
config->sda_hold = ic_clk * DEFAULT_SDA_HOLD_TIME / KHz;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int lpss_i2c_set_speed(unsigned bus, enum i2c_speed speed)
|
|
|
|
{
|
|
|
|
struct lpss_i2c_regs *regs;
|
|
|
|
struct lpss_i2c_speed_config config;
|
|
|
|
uint32_t control;
|
|
|
|
|
|
|
|
/* Clock must be provided by Kconfig */
|
|
|
|
regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus);
|
|
|
|
if (!regs || !speed)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
control = read32(®s->control);
|
|
|
|
control &= ~CONTROL_SPEED_MASK;
|
|
|
|
|
|
|
|
if (speed >= I2C_SPEED_FAST_PLUS) {
|
|
|
|
/* High and Fast-Plus speed share config registers */
|
|
|
|
control |= CONTROL_SPEED_HS;
|
|
|
|
} else if (speed >= I2C_SPEED_FAST) {
|
|
|
|
/* Fast speed */
|
|
|
|
control |= CONTROL_SPEED_FS;
|
|
|
|
} else {
|
|
|
|
/* Standard speed */
|
|
|
|
control |= CONTROL_SPEED_SS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Generate speed config based on clock */
|
|
|
|
if (lpss_i2c_gen_speed_config(speed, &config) < 0)
|
|
|
|
return -1;
|
|
|
|
|
2016-06-07 22:40:11 +02:00
|
|
|
/* Select this speed in the control register */
|
|
|
|
write32(®s->control, control);
|
|
|
|
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
/* Write the speed config that was generated earlier */
|
|
|
|
lpss_i2c_set_speed_config(bus, &config);
|
|
|
|
|
|
|
|
return 0;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
int lpss_i2c_init(unsigned bus, enum i2c_speed speed)
|
2016-06-07 22:40:11 +02:00
|
|
|
{
|
|
|
|
struct lpss_i2c_regs *regs;
|
|
|
|
|
|
|
|
regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus);
|
|
|
|
if (!regs) {
|
|
|
|
printk(BIOS_ERR, "I2C bus %u base address not found\n", bus);
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
return -1;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (lpss_i2c_disable(regs) < 0) {
|
|
|
|
printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus);
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
return -1;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Put controller in master mode with restart enabled */
|
|
|
|
write32(®s->control, CONTROL_MASTER_MODE | CONTROL_SLAVE_DISABLE |
|
|
|
|
CONTROL_RESTART_ENABLE);
|
|
|
|
|
|
|
|
/* Set bus speed to FAST by default */
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
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if (lpss_i2c_set_speed(bus, speed ? : I2C_SPEED_FAST) < 0) {
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printk(BIOS_ERR, "I2C failed to set speed for bus %u\n", bus);
|
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return -1;
|
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}
|
2016-06-07 22:40:11 +02:00
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|
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/* Set RX/TX thresholds to smallest values */
|
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write32(®s->rx_thresh, 0);
|
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write32(®s->tx_thresh, 0);
|
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|
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/* Enable stop detection interrupt */
|
|
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write32(®s->intr_mask, INTR_STAT_STOP_DET);
|
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|
|
|
|
|
|
printk(BIOS_INFO, "LPSS I2C bus %u at 0x%p (%u KHz)\n",
|
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bus, regs, (speed ? : I2C_SPEED_FAST) / KHz);
|
lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-13 19:28:36 +02:00
|
|
|
|
|
|
|
return 0;
|
2016-06-07 22:40:11 +02:00
|
|
|
}
|