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coreboot-kgpe-d16/tests/lib/dimm_info_util-test.c

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tests: Add lib/dimm_info_util-test test case Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-08 16:29:03 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
#include <dimm_info_util.h>
#include <spd.h>
#include <tests/test.h>
lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width() Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-26 09:49:20 +02:00
static void test_smbios_bus_width_to_spd_width_parametrized(smbios_memory_type ddr_type)
tests: Add lib/dimm_info_util-test test case Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-08 16:29:03 +02:00
{
/* Non-ECC variants */
lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width() Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-26 09:49:20 +02:00
assert_int_equal(MEMORY_BUS_WIDTH_64, smbios_bus_width_to_spd_width(ddr_type, 64, 64));
assert_int_equal(MEMORY_BUS_WIDTH_32, smbios_bus_width_to_spd_width(ddr_type, 32, 32));
assert_int_equal(MEMORY_BUS_WIDTH_16, smbios_bus_width_to_spd_width(ddr_type, 16, 16));
assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(ddr_type, 8, 8));
tests: Add lib/dimm_info_util-test test case Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-08 16:29:03 +02:00
/* Incorrect data width. Fallback to 8-bit */
lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width() Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-26 09:49:20 +02:00
assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(ddr_type, 15, 15));
tests: Add lib/dimm_info_util-test test case Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-08 16:29:03 +02:00
/* ECC variants */
lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width() Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-26 09:49:20 +02:00
uint8_t extension_8bits = SPD_ECC_8BIT;
if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5)
extension_8bits = SPD_ECC_8BIT_LP5_DDR5;
assert_int_equal(MEMORY_BUS_WIDTH_64 | extension_8bits,
smbios_bus_width_to_spd_width(ddr_type, 64 + 8, 64));
assert_int_equal(MEMORY_BUS_WIDTH_32 | extension_8bits,
smbios_bus_width_to_spd_width(ddr_type, 32 + 8, 32));
assert_int_equal(MEMORY_BUS_WIDTH_16 | extension_8bits,
smbios_bus_width_to_spd_width(ddr_type, 16 + 8, 16));
assert_int_equal(MEMORY_BUS_WIDTH_8 | extension_8bits,
smbios_bus_width_to_spd_width(ddr_type, 8 + 8, 8));
tests: Add lib/dimm_info_util-test test case Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-08 16:29:03 +02:00
/* Incorrect data width. Fallback to 8-bit */
lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width() Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-26 09:49:20 +02:00
assert_int_equal(MEMORY_BUS_WIDTH_8 | extension_8bits,
smbios_bus_width_to_spd_width(ddr_type, 15 + 8, 15));
}
static void test_smbios_bus_width_to_spd_width(void **state)
{
smbios_memory_type memory_type[] = {
MEMORY_TYPE_DDR2,
MEMORY_TYPE_DDR3,
MEMORY_TYPE_DDR4,
MEMORY_TYPE_DDR5,
MEMORY_TYPE_LPDDR3,
MEMORY_TYPE_LPDDR4,
MEMORY_TYPE_LPDDR5,
};
for (int i = 0; i < ARRAY_SIZE(memory_type); i++) {
print_message("test_smbios_bus_width_to_spd_width_parametrized(%d)\n",
memory_type[i]);
test_smbios_bus_width_to_spd_width_parametrized(memory_type[i]);
}
tests: Add lib/dimm_info_util-test test case Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-08 16:29:03 +02:00
}
static void test_smbios_memory_size_to_mib(void **state)
{
uint32_t extended_size;
uint16_t memory_size;
/* Unknown memory size */
assert_int_equal(0, smbios_memory_size_to_mib(0xFFFF, 0));
assert_int_equal(0, smbios_memory_size_to_mib(0xFFFF, 0xFFFF));
assert_int_equal(0, smbios_memory_size_to_mib(0xFFFF, 87642));
/* 32GiB - 1MiB */
extended_size = 0;
assert_int_equal(extended_size, smbios_memory_size_to_mib(0x7FFF, extended_size));
extended_size = 0xFFFFFFFF;
assert_int_equal(extended_size, smbios_memory_size_to_mib(0x7FFF, extended_size));
extended_size = 0xDEDE6666;
assert_int_equal(extended_size, smbios_memory_size_to_mib(0x7FFF, extended_size));
/* Memory size in KiB when MSB is flipped */
memory_size = 0x0 & 0x8000; /* Zero bytes */
assert_int_equal(0, smbios_memory_size_to_mib(memory_size, 0));
assert_int_equal(0, smbios_memory_size_to_mib(memory_size, 0xFFFFFFFF));
assert_int_equal(0, smbios_memory_size_to_mib(memory_size, 2345568));
memory_size = (31 * KiB) | 0x8000;
assert_int_equal(31, smbios_memory_size_to_mib(memory_size, 0));
assert_int_equal(31, smbios_memory_size_to_mib(memory_size, 0xFFFFFFFF));
assert_int_equal(31, smbios_memory_size_to_mib(memory_size, 72594344));
/* Value in MiB Only when memory size is not 0xFFFF and 0x7FFF and MSB is not set */
memory_size = 32766; /* value in MiB */
assert_int_equal(memory_size, smbios_memory_size_to_mib(memory_size, 0));
assert_int_equal(memory_size, smbios_memory_size_to_mib(memory_size, 0xFFFFFFFF));
assert_int_equal(memory_size, smbios_memory_size_to_mib(memory_size, 694735));
}
static void test_smbios_form_factor_to_spd_mod_type(void **state)
{
/* Form factors defined in coreboot */
const LargestIntegralType udimm_allowed[] = {
SPD_UDIMM, SPD_MICRO_DIMM, SPD_MINI_UDIMM,
};
assert_in_set(smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_DIMM),
udimm_allowed, ARRAY_SIZE(udimm_allowed));
const LargestIntegralType rdimm_allowed[] = { SPD_RDIMM, SPD_MINI_RDIMM };
assert_in_set(smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_RIMM),
rdimm_allowed, ARRAY_SIZE(rdimm_allowed));
assert_int_equal(SPD_SODIMM,
smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_SODIMM));
const smbios_memory_form_factor undefined_factors[] = {
MEMORY_FORMFACTOR_OTHER,
MEMORY_FORMFACTOR_UNKNOWN,
MEMORY_FORMFACTOR_SIMM,
MEMORY_FORMFACTOR_SIP,
MEMORY_FORMFACTOR_CHIP,
MEMORY_FORMFACTOR_DIP,
MEMORY_FORMFACTOR_ZIP,
MEMORY_FORMFACTOR_PROPRIETARY_CARD,
MEMORY_FORMFACTOR_TSOP,
MEMORY_FORMFACTOR_ROC,
MEMORY_FORMFACTOR_SRIMM,
MEMORY_FORMFACTOR_FBDIMM,
MEMORY_FORMFACTOR_DIE,
};
for (int i = 0; i < ARRAY_SIZE(undefined_factors); ++i) {
assert_int_equal(SPD_UNDEFINED,
smbios_form_factor_to_spd_mod_type(undefined_factors[i]));
}
}
int main(void)
{
const struct CMUnitTest tests[] = {
cmocka_unit_test(test_smbios_bus_width_to_spd_width),
cmocka_unit_test(test_smbios_memory_size_to_mib),
cmocka_unit_test(test_smbios_form_factor_to_spd_mod_type),
};
tests: Improve test output readability When running multiple tests, e.g. by using unit-tests target, it is hard to differentiate, which output comes from which file and/or configuration. This patch makes the output easier to analyze and understand by using new wrapper macro cb_run_group_tests(). This macro uses __TEST_NAME__ value (containing test path and Makefile test name) as a group name when calling cmocka group runner. Example: Test path: tests/lib/ Makefile test name: cbmem_stage_cache-test Test group array name: tests Result: tests/lib/cbmem_stage_cache-test(tests) Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-08-25 16:27:35 +02:00
return cb_run_group_tests(tests, NULL, NULL);
tests: Add lib/dimm_info_util-test test case Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-08 16:29:03 +02:00
}