76 lines
1.9 KiB
Plaintext
76 lines
1.9 KiB
Plaintext
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This file defines the processor and performance state capability
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* for each core in the system. It is included into the DSDT for each
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* core. It assumes that each core of the system has the same performance
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* characteristics.
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*/
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/*
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DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
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{
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Scope (\_PR) {
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Processor(CPU0,0,0x808,0x06) {
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#include "cpstate.asl"
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}
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Processor(CPU1,1,0x0,0x0) {
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#include "cpstate.asl"
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}
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Processor(CPU2,2,0x0,0x0) {
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#include "cpstate.asl"
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}
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Processor(CPU3,3,0x0,0x0) {
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#include "cpstate.asl"
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}
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}
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*/
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/* P-state support: The maximum number of P-states supported by the */
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/* CPUs we'll use is 6. */
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/* Get from AMI BIOS. */
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Name(_PSS, Package(){
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Package ()
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{
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0x00000AF0,
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0x0000BF81,
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0x00000002,
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0x00000002,
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0x00000000,
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0x00000000
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},
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Package ()
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{
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0x00000578,
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0x000076F2,
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0x00000002,
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0x00000002,
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0x00000001,
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0x00000001
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}
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})
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Name(_PCT, Package(){
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
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})
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Method(_PPC, 0){
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Return(0)
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}
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