2014-06-30 23:37:13 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA132_CCPLEX_H__
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#define __SOC_NVIDIA_TEGRA132_CCPLEX_H__
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2014-08-22 17:24:27 +02:00
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#include <stdint.h>
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2014-06-30 23:37:13 +02:00
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#define MTS_LOAD_ADDRESS 0x82000000
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2014-07-10 19:50:27 +02:00
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/* Prepare the clocks and rails to start the cpu. */
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void ccplex_cpu_prepare(void);
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2014-06-30 23:37:13 +02:00
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/* Loads the MTS microcode. Return 0 on success, < 0 on error. */
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int ccplex_load_mts(void);
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2014-07-10 19:50:27 +02:00
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/* Start cpu0 and have it start executing at entry_addr */
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void ccplex_cpu_start(void *entry_addr);
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2014-06-30 23:37:13 +02:00
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#endif /* __SOC_NVIDIA_TEGRA132_CCPLEX_H__ */
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