37 lines
996 B
C
37 lines
996 B
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <soc/heci.h>
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#include <soc/pci_devs.h>
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uint32_t heci_fw_sts(void)
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{
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return pci_read_config32(CSE_DEV, REG_SEC_FW_STS0);
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}
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bool heci_cse_normal(void)
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{
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return ((heci_fw_sts() & MASK_SEC_STATUS) == SEC_STATE_NORMAL);
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}
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bool heci_cse_done(void)
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{
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return (!!(heci_fw_sts() & MASK_SEC_FIRMWARE_COMPLETE));
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}
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