65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <reset.h>
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#include <soc/addressmap.h>
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#include <soc/wdt.h>
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static struct mt8173_wdt_regs * const mt8173_wdt = (void *)RGU_BASE;
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int mtk_wdt_init(void)
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{
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uint32_t wdt_sta;
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/* Write Mode register will clear status register */
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wdt_sta = read32(&mt8173_wdt->wdt_status);
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printk(BIOS_INFO, "WDT: Last reset was ");
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if (wdt_sta & MTK_WDT_STA_HW_RST)
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printk(BIOS_INFO, "hardware watchdog\n");
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else if (wdt_sta & MTK_WDT_STA_SW_RST)
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printk(BIOS_INFO, "normal software reboot\n");
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else if (wdt_sta & MTK_WDT_STA_SPM_RST)
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printk(BIOS_INFO, "SPM reboot\n");
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else if (!wdt_sta)
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printk(BIOS_INFO, "cold boot\n");
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else
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printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta);
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/* Config watchdog reboot mode:
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* Clearing bits:
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* DUAL_MODE & IRQ: trigger reset instead of irq then reset.
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* EXT_POL: select watchdog output signal as active low.
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* ENABLE: disable watchdog on initialization.
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* Setting bit EXTEN to enable watchdog output.
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*/
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clrsetbits_le32(&mt8173_wdt->wdt_mode,
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MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
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MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
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MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
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return wdt_sta;
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}
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void hard_reset(void)
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{
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write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
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while (1)
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;
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}
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