2018-10-31 18:42:59 +01:00
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H
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#define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H
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2014-10-28 23:43:20 +01:00
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void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number);
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void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus);
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2018-10-31 18:42:59 +01:00
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#endif
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