2007-04-05 00:45:58 +02:00
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/*
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* flash rom utility: enable flash writes (board specific)
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*
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* Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007 Luc Verhaegen <libv@skynet.be>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2
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*
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*/
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/*
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* Contains the board specific flash enables.
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*/
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdint.h>
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#include <string.h>
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#include "flash.h"
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#include "debug.h"
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2007-05-03 12:09:23 +02:00
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static int board_iwill_dk8_htx(const char *name)
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{
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/* Extended function index register, either 0x2e or 0x4e. */
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#define EFIR 0x2e
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/* Extended function data register, one plus the index reg. */
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#define EFDR EFIR + 1
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char b;
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/* Disable the flash write protect (which is connected to the
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* Winbond W83627HF GPIOs).
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*/
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outb(0x87, EFIR); /* Sequence to unlock extended functions */
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outb(0x87, EFIR);
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/* Activate logical device. */
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outb(0x7, EFIR);
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outb(8, EFDR);
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/* Set GPIO regs. */
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outb(0x2b, EFIR); /* GPIO multiplexed pin reg. */
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b = inb(EFDR) | 0xd0;
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outb(0x2b, EFIR);
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outb(b, EFDR);
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outb(0x30, EFIR); /* GPIO2 */
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b = inb(EFDR) | 0x01;
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outb(0x30, EFIR);
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outb(b, EFDR);
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outb(0xf0, EFIR); /* IO sel */
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b = inb(EFDR) | 0xef;
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outb(0xf0, EFIR);
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outb(b, EFDR);
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outb(0xf1, EFIR); /* GPIO data reg */
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b = inb(EFDR) | 0x16;
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outb(0xf1, EFIR);
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outb(b, EFDR);
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outb(0xf2, EFIR); /* GPIO inversion reg */
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b = inb(EFDR) | 0x00;
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outb(0xf2, EFIR);
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outb(b, EFDR);
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/* Lock extended functions again. */
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outb(0xaa, EFIR); /* Command to exit extended functions */
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return 0;
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}
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2007-04-05 00:45:58 +02:00
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/*
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* Match on pci-ids, no report received, just data from the mainboard
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* specific code:
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* main: 0x1022:0x746B, which is the SMBUS controller.
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* card: 0x1022:0x36C0...
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*/
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static int board_agami_aruma(char *name)
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{
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/* Extended function index register, either 0x2e or 0x4e */
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#define EFIR 0x2e
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/* Extended function data register, one plus the index reg. */
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#define EFDR EFIR + 1
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char b;
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/* Disable the flash write protect. The flash write protect is
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* connected to the WinBond w83627hf GPIO 24.
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*/
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outb(0x87, EFIR); /* sequence to unlock extended functions */
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outb(0x87, EFIR);
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outb(0x20, EFIR); /* SIO device ID register */
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b = inb(EFDR);
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printf_debug("\nW83627HF device ID = 0x%x\n",b);
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if (b != 0x52) {
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fprintf(stderr, "\nIncorrect device ID, aborting write protect disable\n");
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return -1;
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}
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outb(0x2b, EFIR); /* GPIO multiplexed pin reg. */
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b = inb(EFDR) | 0x10;
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outb(0x2b, EFIR);
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outb(b, EFDR); /* select GPIO 24 instead of WDTO */
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outb(0x7, EFIR); /* logical device select */
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outb(0x8, EFDR); /* point to device 8, GPIO port 2 */
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outb(0x30, EFIR); /* logic device activation control */
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outb(0x1, EFDR); /* activate */
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outb(0xf0, EFIR); /* GPIO 20-27 I/O selection register */
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b = inb(EFDR) & ~0x10;
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outb(0xf0, EFIR);
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outb(b, EFDR); /* set GPIO 24 as an output */
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outb(0xf1, EFIR); /* GPIO 20-27 data register */
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b = inb(EFDR) | 0x10;
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outb(0xf1, EFIR);
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outb(b, EFDR); /* set GPIO 24 */
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outb(0xaa, EFIR); /* command to exit extended functions */
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return 0;
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}
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/*
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* Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
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*
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* We don't need to do this when using linuxbios, GPIO15 is never lowered there.
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*/
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static int board_via_epia_m(char *name)
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{
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struct pci_dev *dev;
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unsigned int base;
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uint8_t val;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8235 ISA Bridge not found.\n");
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return -1;
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}
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/* GPIO12-15 -> output */
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val = pci_read_byte(dev, 0xE4);
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val |= 0x10;
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pci_write_byte(dev, 0xE4, val);
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/* Get Power Management IO address. */
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base = pci_read_word(dev, 0x88) & 0xFF80;
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/* enable GPIO15 which is connected to write protect. */
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val = inb(base + 0x4D);
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val |= 0x80;
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outb(val, base + 0x4D);
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return 0;
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}
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/*
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* Winbond LPC super IO.
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*
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* Raises the ROM MEMW# line.
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*/
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static void w83697_rom_memw_enable(void)
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{
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uint8_t val;
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outb(0x87, 0x2E); /* enable extended functions */
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outb(0x87, 0x2E);
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outb(0x24, 0x2E); /* rom bits live here */
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val = inb(0x2F);
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if (!(val & 0x02)) /* flash rom enabled? */
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outb(val | 0x08, 0x2F); /* enable MEMW# */
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outb(0xAA, 0x2E); /* disable extended functions */
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}
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/*
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* Suited for Asus A7V8X-MX SE and A7V400-MX.
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*
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*/
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static int board_asus_a7v8x_mx(char *name)
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{
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struct pci_dev *dev;
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uint8_t val;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8235 ISA Bridge not found.\n");
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return -1;
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}
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/* This bit is marked reserved actually */
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val = pci_read_byte(dev, 0x59);
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val &= 0x7F;
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pci_write_byte(dev, 0x59, val);
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w83697_rom_memw_enable();
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return 0;
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}
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/*
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* We use 2 sets of ids here, you're free to choose which is which. This
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* to provide a very high degree of certainty when matching a board on
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* the basis of Subsystem/card ids. As not every vendor handles
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* subsystem/card ids in a sane manner.
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*
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* Keep the second set nulled if it should be ignored.
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*
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*/
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struct board_pciid_enable {
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/* Any device, but make it sensible, like the isa bridge. */
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uint16_t first_vendor;
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uint16_t first_device;
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uint16_t first_card_vendor;
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uint16_t first_card_device;
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/* Any device, but make it sensible, like
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* the host bridge. May be NULL
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*/
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uint16_t second_vendor;
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uint16_t second_device;
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uint16_t second_card_vendor;
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uint16_t second_card_device;
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/* From linuxbios table */
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char *lb_vendor;
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char *lb_part;
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char *name;
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int (*enable)(char *name);
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};
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struct board_pciid_enable board_pciid_enables[] = {
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2007-05-03 12:09:23 +02:00
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{ 0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,
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"AGAMI", "ARUMA", "agami Aruma", board_agami_aruma },
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{ 0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01,
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2007-04-05 00:45:58 +02:00
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NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m },
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2007-05-03 12:09:23 +02:00
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{ 0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
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NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx },
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{ 0x1022, 0x7468, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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"iwill", "dk8_htx", "IWILL DK8-HTX", board_iwill_dk8_htx },
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2007-04-05 00:45:58 +02:00
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2007-05-03 12:09:23 +02:00
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{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL } /* Keep this */
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2007-04-05 00:45:58 +02:00
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};
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/*
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* Match boards on linuxbios table gathered vendor and part name.
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* Require main pci-ids to match too as extra safety.
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*
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*/
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static struct board_pciid_enable *
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board_match_linuxbios_name(char *vendor, char *part)
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{
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struct board_pciid_enable *board = board_pciid_enables;
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for (; board->name; board++) {
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if (!board->lb_vendor || strcmp(board->lb_vendor, vendor))
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continue;
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if (!board->lb_part || strcmp(board->lb_part, part))
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continue;
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if (!pci_dev_find(board->first_vendor, board->first_device))
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continue;
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if (board->second_vendor &&
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!pci_dev_find(board->second_vendor, board->second_device))
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continue;
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return board;
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}
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return NULL;
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}
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/*
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* Match boards on pci ids and subsystem ids.
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* Second set of ids can be main only or missing completely.
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*/
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static struct board_pciid_enable *board_match_pci_card_ids(void)
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{
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struct board_pciid_enable *board = board_pciid_enables;
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for (; board->name; board++) {
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if (!board->first_card_vendor || !board->first_card_device)
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continue;
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if (!pci_card_find(board->first_vendor, board->first_device,
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board->first_card_vendor,
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board->first_card_device))
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continue;
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if (board->second_vendor) {
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if (board->second_card_vendor) {
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if (!pci_card_find(board->second_vendor,
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board->second_device,
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board->second_card_vendor,
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board->second_card_device))
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continue;
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} else {
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if (!pci_dev_find(board->second_vendor,
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board->second_device))
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continue;
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}
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}
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return board;
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}
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return NULL;
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}
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/*
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*
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*/
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int board_flash_enable(char *vendor, char *part)
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{
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struct board_pciid_enable *board = NULL;
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int ret = 0;
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if (vendor && part)
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board = board_match_linuxbios_name(vendor, part);
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if (!board)
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board = board_match_pci_card_ids();
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if (board) {
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printf("Found board \"%s\": Enabling flash write... ",
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board->name);
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ret = board->enable(board->name);
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if (ret)
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printf("Failed!\n");
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else
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printf("OK.\n");
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}
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return ret;
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}
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