coreboot-kgpe-d16/src/mainboard/amd/mahogany_fam10/Kconfig

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The code can run on the Mahogany board, which is one of sample boards made by AMD. Its major features are: CPU: * AMD AM2+ * AMD Athlon 64 x2 * AMD Athlon 64 FX * AMD Athlon 64 * AMD Sempron CPUs System Chipset: * RS780E * SB700 On Board Chipset: * BIOS - SPI * Azalia CODEC - Realtek ALC888 * LPC SuperIO - ITE8718F(GX). * LAN - REALTEK 8111C * TPM - SLB9635TT1.2 Main Memory: * DDR II * 4 (Max 4GB) Expansion Slots: * PCI Express X16 slot*2 (PCI-E X8 Bus) * PCI Express X4 Slot*1 Intersil PWM: * Controller - Intersil 6323 Note: 1. The only difference to mahogany is the CPU is changed to K8 family 10. 2. The main structure of the code is based on serengeti_cheetah_fam10. I am a rookie to fam10. I am still confused about CONFIG_HT_CHAIN_UNITID_BASE and CONFIG_HT_CHAIN_END_UNITID_BASE. I set them as the way dbm690t does. And I have to modify the some fam10 code (see the patch ht_chain_unitid_base.patch). I dont know how to solve this. Please help. Updated findings: In h3finit.c, the code goes the AMD_CB_ManualBUIDSwapList(). The swaplist is {0x00, 0x00, 0xFF, 0x00, 0xFF}. I am trying to find the meaning of the list. The amdht wrapper needs to modify definitely. 3. With fam10 processor, the HT link can work in HT3. 4. The ACPI _PSS table is set staticly. The auto configuaration process doesnt seem to work correctly. 5. Currently the fam10 code in coreboot doesn't support DDR3. If you happen to get a board with DDR3 and you don't have the patience to wait, please find another board with DDR2. 6. It will take "Uncompressing image to RAM" about 1 minute. I know it is a issue for a long time. I disable the compressing currently. When the problem is fixed, we can re-enable it. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16 02:53:10 +01:00
config BOARD_AMD_MAHOGANY_FAM10
bool "Mahogany (Fam10)"
select ARCH_X86
select CPU_AMD_SOCKET_AM2R2
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
select SOUTHBRIDGE_AMD_SB700
select SUPERIO_ITE_IT8718F
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select USE_PRINTK_IN_CAR
select HAVE_MAINBOARD_RESOURCES
select USE_DCACHE_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select GENERATE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select ENABLE_APIC_EXT_ID
select TINY_BOOTBLOCK
select GFXUMA
config MAINBOARD_DIR
string
default amd/mahogany_fam10
depends on BOARD_AMD_MAHOGANY_FAM10
config APIC_ID_OFFSET
hex
default 0x0
depends on BOARD_AMD_MAHOGANY_FAM10
config MAINBOARD_PART_NUMBER
string
default "Mahogany (Fam10)"
depends on BOARD_AMD_MAHOGANY_FAM10
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
depends on BOARD_AMD_MAHOGANY_FAM10
config MAX_CPUS
int
default 8
depends on BOARD_AMD_MAHOGANY_FAM10
config MAX_PHYSICAL_CPUS
int
default 2
depends on BOARD_AMD_MAHOGANY_FAM10
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
depends on BOARD_AMD_MAHOGANY_FAM10
config MEM_TRAIN_SEQ
int
default 2
depends on BOARD_AMD_MAHOGANY_FAM10
config SB_HT_CHAIN_ON_BUS0
int
default 1
depends on BOARD_AMD_MAHOGANY_FAM10
config HT_CHAIN_END_UNITID_BASE
hex
default 0x1
depends on BOARD_AMD_MAHOGANY_FAM10
config HT_CHAIN_UNITID_BASE
hex
default 0x0
depends on BOARD_AMD_MAHOGANY_FAM10
config IRQ_SLOT_COUNT
int
default 11
depends on BOARD_AMD_MAHOGANY_FAM10
config AMD_UCODE_PATCH_FILE
string
default "mc_patch_01000095.h"
depends on BOARD_AMD_MAHOGANY_FAM10
config RAMTOP
hex
default 0x2000000
depends on BOARD_AMD_MAHOGANY_FAM10
config HEAP_SIZE
hex
default 0xc0000
depends on BOARD_AMD_MAHOGANY_FAM10
config ACPI_SSDTX_NUM
int
default 0
The code can run on the Mahogany board, which is one of sample boards made by AMD. Its major features are: CPU: * AMD AM2+ * AMD Athlon 64 x2 * AMD Athlon 64 FX * AMD Athlon 64 * AMD Sempron CPUs System Chipset: * RS780E * SB700 On Board Chipset: * BIOS - SPI * Azalia CODEC - Realtek ALC888 * LPC SuperIO - ITE8718F(GX). * LAN - REALTEK 8111C * TPM - SLB9635TT1.2 Main Memory: * DDR II * 4 (Max 4GB) Expansion Slots: * PCI Express X16 slot*2 (PCI-E X8 Bus) * PCI Express X4 Slot*1 Intersil PWM: * Controller - Intersil 6323 Note: 1. The only difference to mahogany is the CPU is changed to K8 family 10. 2. The main structure of the code is based on serengeti_cheetah_fam10. I am a rookie to fam10. I am still confused about CONFIG_HT_CHAIN_UNITID_BASE and CONFIG_HT_CHAIN_END_UNITID_BASE. I set them as the way dbm690t does. And I have to modify the some fam10 code (see the patch ht_chain_unitid_base.patch). I dont know how to solve this. Please help. Updated findings: In h3finit.c, the code goes the AMD_CB_ManualBUIDSwapList(). The swaplist is {0x00, 0x00, 0xFF, 0x00, 0xFF}. I am trying to find the meaning of the list. The amdht wrapper needs to modify definitely. 3. With fam10 processor, the HT link can work in HT3. 4. The ACPI _PSS table is set staticly. The auto configuaration process doesnt seem to work correctly. 5. Currently the fam10 code in coreboot doesn't support DDR3. If you happen to get a board with DDR3 and you don't have the patience to wait, please find another board with DDR2. 6. It will take "Uncompressing image to RAM" about 1 minute. I know it is a issue for a long time. I disable the compressing currently. When the problem is fixed, we can re-enable it. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16 02:53:10 +01:00
depends on BOARD_AMD_MAHOGANY_FAM10
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x3060
depends on BOARD_AMD_MAHOGANY_FAM10
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x1022
depends on BOARD_AMD_MAHOGANY_FAM10
config RAMBASE
hex
default 0x200000
depends on BOARD_AMD_MAHOGANY_FAM10
config COMPRESS
hex
default 0
depends on BOARD_AMD_MAHOGANY_FAM10