416 lines
22 KiB
C
416 lines
22 KiB
C
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/*----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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#ifndef __PPC4XX_H__
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#define __PPC4XX_H__
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/*--------------------------------------------------------------------- */
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/* Special Purpose Registers */
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/*--------------------------------------------------------------------- */
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#define srr2 0x3de /* save/restore register 2 */
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#define srr3 0x3df /* save/restore register 3 */
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#define dbsr 0x3f0 /* debug status register */
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#define dbcr0 0x3f2 /* debug control register 0 */
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#define dbcr1 0x3bd /* debug control register 1 */
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#define iac1 0x3f4 /* instruction address comparator 1 */
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#define iac2 0x3f5 /* instruction address comparator 2 */
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#define iac3 0x3b4 /* instruction address comparator 3 */
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#define iac4 0x3b5 /* instruction address comparator 4 */
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#define dac1 0x3f6 /* data address comparator 1 */
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#define dac2 0x3f7 /* data address comparator 2 */
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#define dccr 0x3fa /* data cache control register */
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#define iccr 0x3fb /* instruction cache control register */
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#define esr 0x3d4 /* execption syndrome register */
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#define dear 0x3d5 /* data exeption address register */
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#define evpr 0x3d6 /* exeption vector prefix register */
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#define tsr 0x3d8 /* timer status register */
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#define tcr 0x3da /* timer control register */
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#define pit 0x3db /* programmable interval timer */
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#define sgr 0x3b9 /* storage guarded reg */
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#define dcwr 0x3ba /* data cache write-thru reg*/
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#define sler 0x3bb /* storage little-endian reg */
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#define cdbcr 0x3d7 /* cache debug cntrl reg */
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#define icdbdr 0x3d3 /* instr cache dbug data reg*/
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#define ccr0 0x3b3 /* core configuration register */
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#define dvc1 0x3b6 /* data value compare register 1 */
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#define dvc2 0x3b7 /* data value compare register 2 */
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#define pid 0x3b1 /* process ID */
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#define su0r 0x3bc /* storage user-defined register 0 */
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#define zpr 0x3b0 /* zone protection regsiter */
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#define tbl 0x11c /* time base lower - privileged write */
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#define tbu 0x11d /* time base upper - privileged write */
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#define sprg4r 0x104 /* Special purpose general 4 - read only */
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#define sprg5r 0x105 /* Special purpose general 5 - read only */
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#define sprg6r 0x106 /* Special purpose general 6 - read only */
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#define sprg7r 0x107 /* Special purpose general 7 - read only */
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#define sprg4w 0x114 /* Special purpose general 4 - write only */
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#define sprg5w 0x115 /* Special purpose general 5 - write only */
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#define sprg6w 0x116 /* Special purpose general 6 - write only */
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#define sprg7w 0x117 /* Special purpose general 7 - write only */
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/******************************************************************************
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* Special for PPC405GP
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******************************************************************************/
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/******************************************************************************
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* DMA
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******************************************************************************/
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#define DMA_DCR_BASE 0x100
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#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
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#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
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#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
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#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
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#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
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#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
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#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
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#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
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#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
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#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
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#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
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#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
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#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
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#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
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#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
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#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
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#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
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#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
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#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
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#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
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#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
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#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
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#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
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/******************************************************************************
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* Universal interrupt controller
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******************************************************************************/
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#define UIC_DCR_BASE 0xc0
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#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
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#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
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#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
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#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
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#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
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#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
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#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
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#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
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#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
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/*-----------------------------------------------------------------------------+
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| Universal interrupt controller interrupts
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+-----------------------------------------------------------------------------*/
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#define UIC_UART0 0x80000000 /* UART 0 */
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#define UIC_UART1 0x40000000 /* UART 1 */
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#define UIC_IIC 0x20000000 /* IIC */
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#define UIC_EXT_MAST 0x10000000 /* External Master */
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#define UIC_PCI 0x08000000 /* PCI write to command reg */
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#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
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#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
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#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
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#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
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#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
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#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
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#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
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#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
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#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
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#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
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#define UIC_ENET 0x00010000 /* Ethernet */
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#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
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#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */
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#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
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#define UIC_EXT0 0x00000040 /* External interrupt 0 */
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#define UIC_EXT1 0x00000020 /* External interrupt 1 */
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#define UIC_EXT2 0x00000010 /* External interrupt 2 */
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#define UIC_EXT3 0x00000008 /* External interrupt 3 */
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#define UIC_EXT4 0x00000004 /* External interrupt 4 */
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#define UIC_EXT5 0x00000002 /* External interrupt 5 */
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#define UIC_EXT6 0x00000001 /* External interrupt 6 */
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/******************************************************************************
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* SDRAM Controller
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******************************************************************************/
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#define SDRAM_DCR_BASE 0x10
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#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
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#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
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/* values for memcfga register - indirect addressing of these regs */
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#ifndef CONFIG_405EP
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#define mem_besra 0x00 /* bus error syndrome reg a */
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#define mem_besrsa 0x04 /* bus error syndrome reg set a */
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#define mem_besrb 0x08 /* bus error syndrome reg b */
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#define mem_besrsb 0x0c /* bus error syndrome reg set b */
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#define mem_bear 0x10 /* bus error address reg */
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#endif
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#define mem_mcopt1 0x20 /* memory controller options 1 */
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#define mem_rtr 0x30 /* refresh timer reg */
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#define mem_pmit 0x34 /* power management idle timer */
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#define mem_mb0cf 0x40 /* memory bank 0 configuration */
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#define mem_mb1cf 0x44 /* memory bank 1 configuration */
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#define mem_mb2cf 0x48 /* memory bank 2 configuration */
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#define mem_mb3cf 0x4c /* memory bank 3 configuration */
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#define mem_sdtr1 0x80 /* timing reg 1 */
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#ifndef CONFIG_405EP
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#define mem_ecccf 0x94 /* ECC configuration */
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#define mem_eccerr 0x98 /* ECC error status */
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#endif
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/******************************************************************************
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* Decompression Controller
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******************************************************************************/
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#define DECOMP_DCR_BASE 0x14
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#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
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#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
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/* values for kiar register - indirect addressing of these regs */
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#define kitor0 0x00 /* index table origin register 0 */
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#define kitor1 0x01 /* index table origin register 1 */
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#define kitor2 0x02 /* index table origin register 2 */
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#define kitor3 0x03 /* index table origin register 3 */
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#define kaddr0 0x04 /* address decode definition regsiter 0 */
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#define kaddr1 0x05 /* address decode definition regsiter 1 */
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#define kconf 0x40 /* decompression core config register */
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#define kid 0x41 /* decompression core ID register */
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#define kver 0x42 /* decompression core version # reg */
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#define kpear 0x50 /* bus error addr reg (PLB addr) */
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#define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
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#define kesr0 0x52 /* bus error status reg 0 (R/clear) */
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#define kesr0s 0x53 /* bus error status reg 0 (set) */
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/* There are 0x400 of the following registers, from krom0 to krom3ff*/
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/* Only the first one is given here. */
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#define krom0 0x400 /* SRAM/ROM read/write */
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/******************************************************************************
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* Power Management
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******************************************************************************/
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#define POWERMAN_DCR_BASE 0xb8
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#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
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#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
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#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
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/******************************************************************************
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* Extrnal Bus Controller
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******************************************************************************/
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#define EBC_DCR_BASE 0x12
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#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
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#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
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/* values for ebccfga register - indirect addressing of these regs */
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#define pb0cr 0x00 /* periph bank 0 config reg */
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#define pb1cr 0x01 /* periph bank 1 config reg */
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#define pb2cr 0x02 /* periph bank 2 config reg */
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#define pb3cr 0x03 /* periph bank 3 config reg */
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#define pb4cr 0x04 /* periph bank 4 config reg */
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#define pb5cr 0x05 /* periph bank 5 config reg */
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#define pb6cr 0x06 /* periph bank 6 config reg */
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#define pb7cr 0x07 /* periph bank 7 config reg */
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#define pb0ap 0x10 /* periph bank 0 access parameters */
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#define pb1ap 0x11 /* periph bank 1 access parameters */
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#define pb2ap 0x12 /* periph bank 2 access parameters */
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#define pb3ap 0x13 /* periph bank 3 access parameters */
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#define pb4ap 0x14 /* periph bank 4 access parameters */
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#define pb5ap 0x15 /* periph bank 5 access parameters */
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#define pb6ap 0x16 /* periph bank 6 access parameters */
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#define pb7ap 0x17 /* periph bank 7 access parameters */
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#define pbear 0x20 /* periph bus error addr reg */
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#define pbesr0 0x21 /* periph bus error status reg 0 */
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#define pbesr1 0x22 /* periph bus error status reg 1 */
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#define epcr 0x23 /* external periph control reg */
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/******************************************************************************
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* Control
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******************************************************************************/
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#define CNTRL_DCR_BASE 0x0b0
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#define CPC0_PLLMR (CNTRL_DCR_BASE+0x0) /* PLL mode register */
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#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
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#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
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#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* strap register */
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#define ecr (0xaa) /* edge conditioner register (405gpr) */
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/* Bit definitions */
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#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
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#define PLLMR_FWD_DIV_BYPASS 0xE0000000
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#define PLLMR_FWD_DIV_3 0xA0000000
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#define PLLMR_FWD_DIV_4 0x80000000
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#define PLLMR_FWD_DIV_6 0x40000000
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#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
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#define PLLMR_FB_DIV_1 0x02000000
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#define PLLMR_FB_DIV_2 0x04000000
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#define PLLMR_FB_DIV_3 0x06000000
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#define PLLMR_FB_DIV_4 0x08000000
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#define PLLMR_TUNING_MASK 0x01F80000
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#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
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#define PLLMR_CPU_PLB_DIV_1 0x00000000
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#define PLLMR_CPU_PLB_DIV_2 0x00020000
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#define PLLMR_CPU_PLB_DIV_3 0x00040000
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#define PLLMR_CPU_PLB_DIV_4 0x00060000
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#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
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#define PLLMR_OPB_PLB_DIV_1 0x00000000
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#define PLLMR_OPB_PLB_DIV_2 0x00008000
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#define PLLMR_OPB_PLB_DIV_3 0x00010000
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#define PLLMR_OPB_PLB_DIV_4 0x00018000
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#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
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#define PLLMR_PCI_PLB_DIV_1 0x00000000
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#define PLLMR_PCI_PLB_DIV_2 0x00002000
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#define PLLMR_PCI_PLB_DIV_3 0x00004000
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#define PLLMR_PCI_PLB_DIV_4 0x00006000
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#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
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#define PLLMR_EXB_PLB_DIV_2 0x00000000
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#define PLLMR_EXB_PLB_DIV_3 0x00000800
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#define PLLMR_EXB_PLB_DIV_4 0x00001000
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#define PLLMR_EXB_PLB_DIV_5 0x00001800
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/* definitions for PPC405GPr (new mode strapping) */
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#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
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#define PSR_PLL_FWD_MASK 0xC0000000
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#define PSR_PLL_FDBACK_MASK 0x30000000
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#define PSR_PLL_TUNING_MASK 0x0E000000
|
||
|
|
#define PSR_PLB_CPU_MASK 0x01800000
|
||
|
|
#define PSR_OPB_PLB_MASK 0x00600000
|
||
|
|
#define PSR_PCI_PLB_MASK 0x00180000
|
||
|
|
#define PSR_EB_PLB_MASK 0x00060000
|
||
|
|
#define PSR_ROM_WIDTH_MASK 0x00018000
|
||
|
|
#define PSR_ROM_LOC 0x00004000
|
||
|
|
#define PSR_PCI_ASYNC_EN 0x00001000
|
||
|
|
#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
|
||
|
|
#define PSR_PCI_ARBIT_EN 0x00000400
|
||
|
|
#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* PLL Voltage Controlled Oscillator (VCO) definitions
|
||
|
|
* Maximum and minimum values (in MHz) for correct PLL operation.
|
||
|
|
*/
|
||
|
|
#define VCO_MIN 400
|
||
|
|
#define VCO_MAX 800
|
||
|
|
|
||
|
|
/******************************************************************************
|
||
|
|
* Memory Access Layer
|
||
|
|
******************************************************************************/
|
||
|
|
#define MAL_DCR_BASE 0x180
|
||
|
|
#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
|
||
|
|
#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
|
||
|
|
#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
|
||
|
|
#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
|
||
|
|
#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
|
||
|
|
#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
|
||
|
|
#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
|
||
|
|
#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
|
||
|
|
#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
|
||
|
|
#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
|
||
|
|
#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
|
||
|
|
#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
|
||
|
|
#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
|
||
|
|
#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
|
||
|
|
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
|
||
|
|
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------------
|
||
|
|
| IIC Register Offsets
|
||
|
|
'----------------------------------------------------------------------------*/
|
||
|
|
#define IICMDBUF 0x00
|
||
|
|
#define IICSDBUF 0x02
|
||
|
|
#define IICLMADR 0x04
|
||
|
|
#define IICHMADR 0x05
|
||
|
|
#define IICCNTL 0x06
|
||
|
|
#define IICMDCNTL 0x07
|
||
|
|
#define IICSTS 0x08
|
||
|
|
#define IICEXTSTS 0x09
|
||
|
|
#define IICLSADR 0x0A
|
||
|
|
#define IICHSADR 0x0B
|
||
|
|
#define IICCLKDIV 0x0C
|
||
|
|
#define IICINTRMSK 0x0D
|
||
|
|
#define IICXFRCNT 0x0E
|
||
|
|
#define IICXTCNTLSS 0x0F
|
||
|
|
#define IICDIRECTCNTL 0x10
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------------
|
||
|
|
| UART Register Offsets
|
||
|
|
'----------------------------------------------------------------------------*/
|
||
|
|
#define DATA_REG 0x00
|
||
|
|
#define DL_LSB 0x00
|
||
|
|
#define DL_MSB 0x01
|
||
|
|
#define INT_ENABLE 0x01
|
||
|
|
#define FIFO_CONTROL 0x02
|
||
|
|
#define LINE_CONTROL 0x03
|
||
|
|
#define MODEM_CONTROL 0x04
|
||
|
|
#define LINE_STATUS 0x05
|
||
|
|
#define MODEM_STATUS 0x06
|
||
|
|
#define SCRATCH 0x07
|
||
|
|
|
||
|
|
/******************************************************************************
|
||
|
|
* On Chip Memory
|
||
|
|
******************************************************************************/
|
||
|
|
#define OCM_DCR_BASE 0x018
|
||
|
|
#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
|
||
|
|
#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
|
||
|
|
#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
|
||
|
|
#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
|
||
|
|
|
||
|
|
/******************************************************************************
|
||
|
|
* GPIO macro register defines
|
||
|
|
******************************************************************************/
|
||
|
|
#define GPIO_BASE 0xEF600700
|
||
|
|
#define GPIO0_OR (GPIO_BASE+0x0)
|
||
|
|
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||
|
|
#define GPIO0_OSRH (GPIO_BASE+0x8)
|
||
|
|
#define GPIO0_OSRL (GPIO_BASE+0xC)
|
||
|
|
#define GPIO0_TSRH (GPIO_BASE+0x10)
|
||
|
|
#define GPIO0_TSRL (GPIO_BASE+0x14)
|
||
|
|
#define GPIO0_ODR (GPIO_BASE+0x18)
|
||
|
|
#define GPIO0_IR (GPIO_BASE+0x1C)
|
||
|
|
#define GPIO0_RR1 (GPIO_BASE+0x20)
|
||
|
|
#define GPIO0_RR2 (GPIO_BASE+0x24)
|
||
|
|
#define GPIO0_ISR1H (GPIO_BASE+0x30)
|
||
|
|
#define GPIO0_ISR1L (GPIO_BASE+0x34)
|
||
|
|
#define GPIO0_ISR2H (GPIO_BASE+0x38)
|
||
|
|
#define GPIO0_ISR2L (GPIO_BASE+0x3C)
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Macro for accessing the indirect EBC register
|
||
|
|
*/
|
||
|
|
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
|
||
|
|
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
|
||
|
|
|
||
|
|
struct ppc4xx_sys_info
|
||
|
|
{
|
||
|
|
unsigned long pllFwdDiv;
|
||
|
|
unsigned long pllFwdDivB;
|
||
|
|
unsigned long pllFbkDiv;
|
||
|
|
unsigned long pllPlbDiv;
|
||
|
|
unsigned long pllPciDiv;
|
||
|
|
unsigned long pllExtBusDiv;
|
||
|
|
unsigned long pllOpbDiv;
|
||
|
|
unsigned long freqVCOMhz; /* in MHz */
|
||
|
|
unsigned long freqProcessor;
|
||
|
|
unsigned long freqPLB;
|
||
|
|
unsigned long freqPCI;
|
||
|
|
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
|
||
|
|
unsigned long pciClkSync; /* PCI clock is synchronous */
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* __PPC4XX_H__ */
|
||
|
|
|