2023-05-13 00:50:27 +02:00
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Upcoming release - coreboot 4.21
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========================================================================
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2023-08-21 03:02:27 +02:00
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The 4.21 release is scheduled for August 21st, 2023
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2023-05-13 00:50:27 +02:00
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2023-08-21 03:02:27 +02:00
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In the past quarter year, the coreboot project has gotten over 1200 new
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patches from around 140 authors, 20 of whom contributed for the first
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time.
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2023-05-13 00:50:27 +02:00
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2023-08-21 03:02:27 +02:00
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Thank you to all of our donors, the code contributors, the people who
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take time to review all of those patches and all of the people who care
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about the coreboot project. There have been a number of new companies
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starting to use coreboot recently, and we appreciate all of the
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contributions and support.
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### Upcoming switch from master branch to main branch
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Historically, the initial branch that was created in a new git
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repository was named ‘master’. In line with many other projects,
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coreboot has decided to switch away from this name and use the name
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‘main’ instead. You can read about the initial reasoning on the SFC’s
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website: https://sfconservancy.org/news/2020/jun/23/gitbranchname/
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At some point before the 4.22 release, coreboot will be switching from
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the master branch to the main branch. This shouldn’t be a difficult
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change for most people, as everyone will just have to rebase on top of
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a different branch name.
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We’ve already created the main branch, and it is currently synced with
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the master branch. Please update any scripts to point to main instead
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of master.
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At the point of the changeover, we will move all patches in gerrit to
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the main branch and disable pushes to the master branch.
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After the switch, we will sync the main branch to the master branch for
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a while to give people a little more time to update any scripts that
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are currently pointed at the master branch. Note that this update will
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probably be done just once per day, and the frequency of updates will
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be decreased over time. We plan to stop updating the master branch
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following the 4.22 release.
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2023-05-13 00:50:27 +02:00
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Significant or interesting changes
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----------------------------------
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2023-08-21 03:02:27 +02:00
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### lib: Support localized text of memory_training_desc in ux_locales.c
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Most of the text in coreboot is for logging, and does not use
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localization. There are however, some bits of text that can be
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presented to the user, and this patch supplies a method to localize
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them.
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To support the localized text, we need to get the locale id by vboot
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APIs and read raw string content file: preram_locales located at either
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RO or RW.
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The preram_locales file follows the format:
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[PRERAM_LOCALES_VERSION_BYTE (\x01)]
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[string_name_1] [\x00]
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[locale_id_1] [\x00] [localized_string_1] [\x00]
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[locale_id_2] [\x00] [localized_string_2] …
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[\x01]
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[string_name_2] [\x00] ...
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This code will search for the correct localized string that its string
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name is `memory_training_desc` and its locale ID matches the ID vb2api
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returns. If no valid string found, we will try to display in English
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(locale ID 0).
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### Improved the bootsplash support
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The JPEG decoder, that was added many years ago to display a bootsplash
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in coreboot, has a few quirks. People used to do some voodoo with GIMP
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to convert images to the right format, but we can also achieve the same
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with ImageMagick's `convert`. The currently known constraints are:
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* The framebuffer's color format is ignored,
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* only YCC 4:2:0 color sampling is supported, and
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* width and height have to be a multiple of 16 pixels.
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Beside that, we can only display the bootsplash if it completely fits
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into the framebuffer. As the latter's size is often decided at runtime,
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we can't do much more than offering an option to set a specific size.
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The build system has been extended so that the necessary adjustments to
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the picture can be done by it and several options have been added to
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Kconfig.
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### libpayload/uhci: Re-write UHCI RH driver w/ generic_hub API
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This is a complete rewrite of the UHCI root-hub driver, based on the
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xHCI one. We are doing things by the book as far as possible. One
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special case is uhci_rh_reset_port() which does the reset sequencing
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that usually the hardware would do.
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This abandons some quirks of the old driver:
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* Ports are not disabled/re-enabled for every attachment anymore.
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* We solely rely on the Connect Status Change bit to track changes.
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* Further status changes are now deferred to the next polling round.
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### linux_trampoline: Handle coreboot framebuffer & 64-bit addresses
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Translate the coreboot framebuffer info from coreboot tables to the
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Linux zero page.
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To support full 64-bit addresses, there is a new field `ext_lfb_base`
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since Linux 4.1. It is unclear, however, how a loader is supposed to
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know if the kernel is compatible with this. Filling these previously
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reserved bits doesn't hurt, but an old kernel would probably ignore
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them and not know that it's handling a clipped, invalid address. So we
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play safe, and only allow 64-bit addresses for kernels after the 2.15
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version bump of the boot protocol.
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### arch/x86: Don't allow hw floating point operations
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Even though coreboot does not allow floating point operations, some
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compilers like clang generate code using hw floating point registers,
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e.g. SSE %XMMx registers on 64bit code by default. Floating point
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operations need to be enabled in hardware for this to work (CR4). Also
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in SMM we explicitly need to save and restore floating point registers
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for this reason. If we instruct the compiler to not generate code with
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FPU ops, this simplifies our code as we can skip that step.
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With clang this reduces the binary size a bit. For instance ramstage
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for emulation/qemu-q35 drops by 4 kB from from 216600 bytes
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decompressed to 212768 bytes.
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Since we now explicitly compile both ramstage and smihandler code
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without floating point operations and associated registers we don't
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need to save/restore floating point registers in SMM.
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The EFER MSR is in the SMM save state and RSM properly restores it.
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Returning to 32bit mode was only done so that fxsave was done in the
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same mode as fxrstor, but this is no longer done.
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### Caching of PCIe 5.0 HSPHY firmware in SPI flash
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This adds the ability to cache the PCIe 5.0 HSPHY firmware in the SPI
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flash. A new flashmap region is created for that purpose. The goal of
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caching is to reduce the dependency on the CSME (Converged Security and
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Management Engine) and the HECI (Host Embedded Controller Interface) IP
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LOAD command which may fail when the CSME is disabled, e.g. soft
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disabled by HECI command or HAP (High Assurance Platform mode). By
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caching that firmware, this allows the PCIe 5.0 root ports to keep
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functioning even if CSME/HECI is not functional.
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2023-05-13 00:50:27 +02:00
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2023-08-21 03:02:27 +02:00
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### Extracting of TPM logs using cbmem tool
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2023-05-25 06:16:48 +02:00
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2023-08-21 03:02:27 +02:00
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CBMEM can contain logs in different forms (at most one is present):
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* coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
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LB_TAG_TPM_CB_LOG)
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* TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
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* TPM2 format (CBMEM_ID_TPM2_TCG_LOG)
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The last two follow specifications by Trusted Computing Group, but
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until now cbmem couldn't print them.
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These changes make the cbmem utility check for existence of TPM1.2/TPM2
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logs in CBMEM and add code necessary for parsing and printing of their
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entries.
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`cbmem -L` for CONFIG_TPM1=y case
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```
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TCPA log:
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Specification: 1.21
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Platform class: PC Client
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TCPA log entry 1:
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PCR: 2
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Event type: Action
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Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
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Event data: FMAP: FMAP
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```
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`cbmem -L` for CONFIG_TPM2=y case
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```
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TPM2 log:
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Specification: 2.00
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Platform class: PC Client
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TPM2 log entry 1:
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PCR: 2
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Event type: Action
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Digests:
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SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
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Event data: FMAP: FMAP
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```
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### soc/amd: read domain resource window configuration from hardware
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Read the MMIO and IO decode windows for the PCI root complex and the
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PCI bus number range decoded to the PCI root complex from the data
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fabric registers and pass the information to the resource allocator so
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it has the correct constraints to do its job. Also generate the
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corresponding ACPI resource producers in the SSDT so that the OS knows
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about this too. This is required for the upcoming USB 4 support.
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Additional coreboot changes
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---------------------------
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* Added SPDX headers to more files to help automated license checking.
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The linter has been enabled to check the Makefiles as well.
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* Cleaned up Kconfig files and source code.
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* Enabled acpigen to generate tables for SPCR (Serial Port Console
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Redirection) and GTDT (Generic Timer Description Table).
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* The resource allocation above the 4GiB boundary has been improved.
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* Most of the code has been adjusted to make use of C99 flexible arrays
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instead of one-element or zero-length arrays.
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* Additional Dockerfiles based on Arch and Alpine Linux have been added
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to build-test with alternate build environments, including musl-libc.
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They are very basic at the moment and not equal to the coreboot-sdk.
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They will be extended in the future.
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* Added support for ITE IT8784E to superiotool.
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* Added support for Intel 700 chipset series to inteltool and a build
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issue with musl–libc has been fixed.
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* Added support for Intel 800 chipset series to ifdtool.
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* The coreboot-sdk container has been extended so that it allows
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extracting the MRC binary from Haswell-based ChromeOS firmware images.
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* From now on POST code preprocessor macros should have a POSTCODE
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prefix following the name of the POST code.
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* The NASM compiler provided by the coreboot toolchain wasn’t properly
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integrated into xcompile and thus it wasn’t used by the build system.
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Instead, it was required to install NASM on the host in order to use
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it. This has been fixed.
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* The time measurement done in abuild got improved and also an issue
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has been fixed when the variant name contains hyphens.
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* The RISC-V code was enabled to build with Clang.
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* Initial work has been done to transform Camelcase options to
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Snakecase.
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* The buildgcc script is now able to just fetch the tarballs if desired,
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which is needed for reproducible build environments for example.
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Changes to external resources
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-----------------------------
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### Toolchain
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* binutils
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* Added binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch
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2023-07-30 21:12:39 +02:00
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* Upgrade IASL from 20221020 to 20230628
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* Upgrade LLVM from 15.0.7 to 16.0.6
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* Upgrade NASM from 2.15.05 to 2.16.01
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2023-08-21 03:02:27 +02:00
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* Added nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch
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2023-06-03 09:51:40 +02:00
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* Upgrade CMake from 3.26.3 to 3.26.4
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2023-07-30 21:12:39 +02:00
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* Upgrade GCC from 11.3.0 to 11.4.0
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2023-08-21 03:02:27 +02:00
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* Added gcc-11.4.0_rv32iafc.patch
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2023-05-25 06:16:48 +02:00
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2023-05-13 00:50:27 +02:00
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2023-08-21 03:02:27 +02:00
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### Git submodule pointers
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#### /3rdparty
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* amd_blobs: Update from commit id 1cd6ea5cc5 to 6a1e1457af (5 commits)
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* arm-trusted-firmware: Update from commit id 4c985e8674 to 37366af8d4
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(851 commits)
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* blobs: Update from commit id 01ba15667f to a8db7dfe82 (14 commits)
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* fsp: Update from commit id 6f2f17f3d3 to 3beceb01f9 (24 commits)
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* intel-microcode: Update from commit id 2be47edc99 to 6f36ebde45 (5
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commits)
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* libgfxinit: Update from commit id 066e52eeaa to a4be8a21b0 (18
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commits)
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* libhwbase: Update from commit id 8be5a82b85 to 584629b9f4 (2 commits)
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* qc_blobs: Update from commit id 33cc4f2fd8 to a252198ec6 (4 commits)
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* vboot: Update from commit id 35f50c3154 to 0c11187c75 (83 commits)
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#### /util
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* goswid: Update from commit id bdd55e4202 to 567a1c99b0 (5 commits)
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* nvidia/cbootimage: Update from commit id 65a6d94dd5 to 80c499ebbe (1
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commit)
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### External payloads
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* Update the depthcharge payload from commit ID 902681db13 to c48613a71c
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* Upgrade EDK2-MrChromebox from version 202304 to version 202306
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* Upgrade SeaBIOS from version 1.16.1 to version 1.16.2
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* Update tint from version 0.05 to version 0.07
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* Update U-Boot from version 2021.07 to version v2023.07
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2023-05-13 00:50:27 +02:00
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2023-08-21 03:02:27 +02:00
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Added mainboards:
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-----------------
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* ByteDance ByteDance bd_egs
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* Google: Craaskov
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* Google: Expresso
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* Google: Karis
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* Google: Karis4ES
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* Google: Pirrha
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* Google: Ponyta
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* Google: Screebo4ES
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* Google: Ovis
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* Google: Ovis4ES
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* Google: Rex EC ISH
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* Google: Rex4ES
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* HP Compaq Elite 8300 USDT
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* HP EliteBook 820 G2
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* IBM SBP1
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* Intel Raptorlake silicon with Alderlake-P RVP
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* Inventec Transformers
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* MSI PRO Z790-P (WIFI)
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* MSI PRO Z790-P (WIFI) DDR4
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* Star Labs Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
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* System76 addw3
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* System76 bonw15
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* System76 darp9
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* System76 galp7
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* System76 gaze17 3050
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* System76 gaze17 3060-b
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* System76 gaze18
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* System76 lemp12
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* System76 oryp11
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* System76 serw13
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2023-05-13 00:50:27 +02:00
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2023-08-21 03:02:27 +02:00
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Removed Mainboards
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------------------
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* Intel Galileo
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Updated SoCs
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------------
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* Removed src/soc/intel/quark
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2023-05-13 00:50:27 +02:00
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Statistics from the 4.20 to the 4.21 release
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--------------------------------------------
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2023-08-21 03:02:27 +02:00
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* Total Commits: 1252
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* Average Commits per day: 12.59
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* Total lines added: 317734
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* Average lines added per commit: 253.78
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* Number of patches adding more than 100 lines: 86
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* Average lines added per small commit: 36.22
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* Total lines removed: 261063
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* Average lines removed per commit: 208.52
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* Total difference between added and removed: 56671
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* Total authors: 143
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* New authors: 21
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2023-05-13 00:50:27 +02:00
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Significant Known and Open Issues
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---------------------------------
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2023-08-21 03:02:27 +02:00
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Issues from the coreboot bugtracker: https://ticket.coreboot.org/
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```eval_rst
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+-----+-----------------------------------------------------------------+
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| # | Subject |
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+=====+=================================================================+
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| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
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+-----+-----------------------------------------------------------------+
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| 495 | Stoney chromebooks not booting PSPSecureOS |
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+-----+-----------------------------------------------------------------+
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| 478 | X200 booting Linux takes a long time with TSC |
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+-----+-----------------------------------------------------------------+
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| 474 | X200s crashes after graphic init with 8GB RAM |
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+-----+-----------------------------------------------------------------+
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| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
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+-----+-----------------------------------------------------------------+
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| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit |
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+-----+-----------------------------------------------------------------+
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| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
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+-----+-----------------------------------------------------------------+
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| 448 | Thinkpad T440P ACPI Battery Value Issues |
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+-----+-----------------------------------------------------------------+
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| 446 | Optiplex 9010 No Post |
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+-----+-----------------------------------------------------------------+
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| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
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+-----+-----------------------------------------------------------------+
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| 427 | x200: Two battery charging issues |
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+-----+-----------------------------------------------------------------+
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| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
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+-----+-----------------------------------------------------------------+
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| 412 | x230 reboots on suspend |
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+-----+-----------------------------------------------------------------+
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| 393 | T500 restarts rather than waking up from suspend |
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+-----+-----------------------------------------------------------------+
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| 350 | I225 PCIe device not detected on Harcuvar |
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+-----+-----------------------------------------------------------------+
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| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
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+-----+-----------------------------------------------------------------+
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```
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coreboot Links and Contact Information
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--------------------------------------
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* Main Web site: https://www.coreboot.org
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* IRC: https://web.libera.chat/#coreboot
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* Downloads: https://coreboot.org/downloads.html
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* Source control: https://review.coreboot.org
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* Documentation: https://doc.coreboot.org
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* Issue tracker: https://ticket.coreboot.org/projects/coreboot
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* Donations: https://coreboot.org/donate.html
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