70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <PlatformMemoryConfiguration.h>
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/*----------------------------------------------------------------------------------------
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* CUSTOMER OVERIDES MEMORY TABLE
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*----------------------------------------------------------------------------------------
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*/
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//reference BKDG Table87: works
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#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
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#define SEED_A 0x54
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#define SEED_B 0x4D
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#define SEED_C 0x45
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#define SEED_D 0x40
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#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
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//4B 41 51
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/*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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WRITE_LEVELING_SEED(
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ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
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F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
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F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
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F15_WL_SEED),
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HW_RXEN_SEED(
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ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
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SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
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SEED_A),
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HW_RXEN_SEED(
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ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
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SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
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SEED_B),
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HW_RXEN_SEED(
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ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
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SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
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SEED_C),
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HW_RXEN_SEED(
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ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
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SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
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SEED_D),
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
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PSO_END
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};
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const struct OEM_HOOK OemCustomize = {
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};
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