67 lines
1.3 KiB
C
67 lines
1.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 4
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*/
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#include <device/mmio.h>
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#include <intelblocks/cfg.h>
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#include <intelpch/lockdown.h>
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#include <soc/pm.h>
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#include <stdint.h>
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static void pmc_lock_pmsync(void)
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{
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uint8_t *pmcbase;
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uint32_t pmsyncreg;
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pmcbase = pmc_mmio_regs();
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pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
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pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
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write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
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}
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static void pmc_lock_abase(void)
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{
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uint8_t *pmcbase;
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uint32_t reg32;
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pmcbase = pmc_mmio_regs();
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reg32 = read32(pmcbase + GEN_PMCON_B);
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reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
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write32(pmcbase + GEN_PMCON_B, reg32);
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}
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static void pmc_lock_smi(void)
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{
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uint8_t *pmcbase;
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uint8_t reg8;
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pmcbase = pmc_mmio_regs();
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reg8 = read8(pmcbase + GEN_PMCON_B);
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reg8 |= SMI_LOCK;
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write8(pmcbase + GEN_PMCON_B, reg8);
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}
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static void pmc_lockdown_cfg(int chipset_lockdown)
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{
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/* PMSYNC */
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pmc_lock_pmsync();
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/* Lock down ABASE and sleep stretching policy */
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pmc_lock_abase();
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
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pmc_lock_smi();
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}
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void soc_lockdown_config(int chipset_lockdown)
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{
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/* PMC lock down configuration */
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pmc_lockdown_cfg(chipset_lockdown);
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}
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