coreboot-kgpe-d16/src/southbridge/intel/i82371eb/i82371eb.c

/*
 * This file is part of the LinuxBIOS project.
 *
 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

/* Datasheet:
 *   - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
 *   - URL: http://www.intel.com/design/intarch/datashts/290562.htm
 *   - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
 *   - Order Number: 290562-001
 */

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include "i82371eb.h"

/**
 * Enable access to all BIOS regions. Do not enable write access to the ROM.
 *
 * XBCS register bits:
 * - Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
 *              FFF00000-FFF7FFFF are forwarded to ISA).
 * - Set bit 7: Extended BIOS Enable (PCI master accesses to
 *              FFF80000-FFFDFFFF are forwarded to ISA).
 * - Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
 *              the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
 *              of 1 Mbyte, or the aliases at the top of 4 Gbyte
 *              (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
 * - Bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
 *
 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
 *
 * @param dev The device to use.
 */
void i82371eb_enable(device_t dev)
{
	uint16_t reg;

	reg = pci_read_config16(dev, XBCS);
	reg |= 0x2c0;
	pci_write_config16(dev, XBCS, reg);
}

struct chip_operations southbridge_intel_i82371eb_ops = {
	CHIP_NAME("Intel 82371EB Southbridge")
	.enable_dev = i82371eb_enable,
};