58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include "pch.h"
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#define PCH_EHCI1_TEMP_BAR0 0xe8000000
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#define PCH_EHCI2_TEMP_BAR0 0xe8000400
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/*
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* Setup USB controller MMIO BAR to prevent the
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* reference code from resetting the controller.
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*
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* The BAR will be re-assigned during device
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* enumeration so these are only temporary.
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*/
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void enable_usb_bar(void)
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{
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device_t usb0 = PCH_EHCI1_DEV;
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device_t usb1 = PCH_EHCI2_DEV;
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u32 cmd;
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/* USB Controller 1 */
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pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
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PCH_EHCI1_TEMP_BAR0);
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cmd = pci_read_config32(usb0, PCI_COMMAND);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config32(usb0, PCI_COMMAND, cmd);
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/* USB Controller 1 */
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pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
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PCH_EHCI1_TEMP_BAR0);
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cmd = pci_read_config32(usb1, PCI_COMMAND);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config32(usb1, PCI_COMMAND, cmd);
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}
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