133 lines
7.0 KiB
Markdown
133 lines
7.0 KiB
Markdown
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# Frequency selection
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## Introduction
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This chapter explains the frequency selection done on Sandybride and Ivybridge.
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## Definitions
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| Symbol | Description | Units | Valid region |
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|---------|-------------------------------------------------------------------|------------|--------------|
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| SCK | DRAM system clock cycle time | s | - |
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| tCK | DRAM system clock cycle time | 1/256th ns | - |
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| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
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| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
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| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
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| MULT | DRAM PLL multiplier | - | [3-12] |
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| XMP | Extreme Memory Profiles | - | - |
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## SPD
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The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
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located on every DIMM is factory program with various timings. One of them
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specifies the maximum clock frequency the DIMM should be used with. The
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operating frequency is stores as fixed point value (tCK), rounded to the next
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smallest supported operating frequency. Some
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[SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
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contains additional and optional
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[XMP](https://de.wikipedia.org/wiki/Extreme_Memory_Profile "Extreme Memory Profile")
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data, that stores so called "performance" modes, that advertises higher clock
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frequencies.
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## XMP profiles
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At time of writing coreboot's raminit is able to parse XMP profile 1 and 2.
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Only **XMP profile 1** is being used in case it advertises:
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* 1.5V operating voltage
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* The channel's installed DIMM count doesn't exceed the XMP coded limit
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In case the XMP profile doesn't fullfill those limits, the regular SPD will be
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used.
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> **Note:** XMP Profiles are supported since coreboot 4.4.
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It is possible to ignore the max DIMM count limit set by XMP profiles.
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By activating Kconfig option `NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS` it is
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possible to install two DIMMs per channel, even if XMP tells you not to do.
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> **Note:** Ignoring XMP Profiles limit is supported since coreboot 4.7.
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## Soft fuses
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Every board manufacturer does program "soft" fuses to indicate the maximum
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DRAM frequency supported. However, those fuses don't set a limit in hardware
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and thus are called "soft" fuses, as it is possible to ignore them.
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> **Note:** Ignoring the fuses might cause system instability !
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On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being
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read. coreboot reads those registers and honors the limit in case the Kconfig
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option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.
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Power users that want to let their RAM run at DRAM's "stock" frequency need to
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enable the Kconfig symbol.
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It is possible to override the soft fuses limit by using a board-specific
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[devicetree](#devicetree) setting.
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> **Note:** Ignoring max mem freq. fuses is supported since coreboot 4.7.
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## <a name="hard_fuses"></a> Hard fuses
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"Hard" fuses are programmed by Intel and limit the maximum frequency that can
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be used on a given CPU/board/chipset. At time of writing there's no register
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to read this limit, before trying to set a given DRAM frequency. The memory PLL
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won't lock, indicating that the chosen memory multiplier isn't available. In
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this case coreboot tries the next smaller memory multiplier until the PLL will
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lock.
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## <a name="devicetree"></a> Devicetree
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The devicetree register ```max_mem_clock_mhz``` overrides the "soft" fuses set
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by the board manufacturer.
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By using this register it's possible to force a minimum operating frequency.
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## Reference clock
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While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also
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supports 100 MHz reference clock. The reference clock is multiplied by the DRAM
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multiplier to select the DRAM frequency (SCK) by the following formula:
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REFCK * MULT = 1 / DCK
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> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
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## Sandy Bride's supported frequencies
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| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
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|------------|-----------|------------------|-------------------------|---------------|
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| 400 | DDR3-800 | 3 | 133 MHz | |
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| 533 | DDR3-1066 | 4 | 133 MHz | |
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| 666 | DDR3-1333 | 5 | 133 MHz | |
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| 800 | DDR3-1600 | 6 | 133 MHz | |
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| 933 | DDR3-1866 | 7 | 133 MHz | |
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| 1066 | DDR3-2166 | 8 | 133 MHz | ||
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## Ivybridge's supported frequencies
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| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
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|------------|-----------|------------------|-------------------------|---------------|
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| 400 | DDR3-800 | 3 | 133 MHz | |
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| 533 | DDR3-1066 | 4 | 133 MHz | |
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| 666 | DDR3-1333 | 5 | 133 MHz | |
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| 800 | DDR3-1600 | 6 | 133 MHz | |
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| 933 | DDR3-1866 | 7 | 133 MHz | |
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| 1066 | DDR3-2166 | 8 | 133 MHz | |
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| 700 | DDR3-1400 | 7 | 100 MHz | '1 |
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| 800 | DDR3-1600 | 8 | 100 MHz | '1 |
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| 900 | DDR3-1800 | 9 | 100 MHz | '1 |
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| 1000 | DDR3-2000 | 10 | 100 MHz | '1 |
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| 1100 | DDR3-2200 | 11 | 100 MHz | '1 |
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| 1200 | DDR3-2400 | 12 | 100 MHz | '1 ||
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> '1: since coreboot 4.6
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## Multiplier selection
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coreboot select the maximum frequency to operate at by the following formula:
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```
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if devicetree's max_mem_clock_mhz > 0:
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freq_max := max_mem_clock_mhz
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else:
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freq_max := soft_fuse_max_mhz
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for i in SPDs:
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freq_max := MIN(freq_max, ddr_spd_max_mhz[i])```
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As you can see, by using DIMMs with different maximum DRAM frequencies, the
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slowest DIMMs' frequency will be selected, to prevent over-clocking it.
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The selected frequency gives the PLL multiplier to operate at. In case the PLL
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locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for
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all DIMMs. At this point it's not possible to change the multiplier again,
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until the system has been powered off. In case the PLL doesn't lock, the next
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smaller multiplier will be used until a working multiplier will be found.
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