coreboot-kgpe-d16/src/mainboard/intel/dg43gt/Kconfig.name

config BOARD_INTEL_DG43GT
	bool "DG43GT"
mb/intel/dg43gt: Add mainboard This mainboard features is an G43 northbridge, ICH10 southbridge and Winbond W83627dhg SuperI/O. This board is impossible to flash internally with vendor bios (BIOS region is WP and other regions like IFD and ME are read only and inaccessible respectively). Due to either ICH10 or board layout it is also impossible to do ISP, which requires desoldering flash chip. To make hacking more easy there is an empty SPI header next to spi flash pads which can be hooked up to a SPI flash. What works: * 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1); * SATA with AHCI * Integrated GPU with option rom (extracted from a Gigabyte vendor bios) * VGA (on DVI) with NGI if patched to use DVI gmbus port for output * PCI * Reboot and S3 resume * Descriptor mode with ME disable straps and ME region absent (no working gbe in this configuration though) * USB. What does not work: * GBE (probably requires working ME); * Analog on DVI port out is shaking, which is not the case with vendor BIOS (setting clockgen on smbus 0x69 like vendor fixes it). * Booting with ME enabled (needs raminit patches for that) Not tested: * Sound; * All the rest. Not coreboot related problems: * Flashing this board with vendor bios is a PITA and requires desoldering flash chip; * In situ programming is not possible. TESTED with SeaBIOS and Linux 4.10.8 Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> 2017-04-12 13:53:08 +02:00			`config BOARD_INTEL_DG43GT`
			`bool "DG43GT"`