2010-09-30 18:55:02 +02:00
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ramstage-y += device.c
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|
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ramstage-y += root_device.c
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2012-08-07 16:12:11 +02:00
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ramstage-y += cpu_device.c
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2010-09-30 18:55:02 +02:00
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ramstage-y += device_util.c
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2012-11-30 01:28:21 +01:00
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ramstage-$(CONFIG_PCI) += pci_device.c
|
2010-09-30 18:55:02 +02:00
|
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ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
|
2011-11-30 21:45:14 +01:00
|
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ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
|
2012-11-30 01:28:21 +01:00
|
|
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ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
|
2011-11-30 21:45:14 +01:00
|
|
|
ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c
|
|
|
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ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
|
2013-08-12 14:07:47 +02:00
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|
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ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c
|
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
|
|
|
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c
|
2012-11-30 01:28:21 +01:00
|
|
|
ramstage-$(CONFIG_PCI) += pci_ops.c
|
2014-02-14 11:45:09 +01:00
|
|
|
ramstage-$(CONFIG_PCI) += pci_early.c
|
2010-09-30 18:55:02 +02:00
|
|
|
ramstage-y += smbus_ops.c
|
2009-08-12 17:00:51 +02:00
|
|
|
|
2014-02-11 18:56:57 +01:00
|
|
|
romstage-y += device_romstage.c
|
|
|
|
|
romstage-$(CONFIG_PCI) += pci_early.c
|
Make the device tree available in the rom stage
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage
We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.
So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
#ifndef __PRE_RAM__
.ops = 0,
#endif
.bus = &_dev7_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
.enabled = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1ae0,
.subsystem_device = 0xc000,
.link_list = NULL,
.sibling = &_dev22,
#ifndef __PRE_RAM__
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_10,
.next=&_dev22
};
Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-01 01:47:25 +02:00
|
|
|
|
2010-06-04 17:55:12 +02:00
|
|
|
subdirs-y += oprom
|
|
|
|
|
|
2010-09-30 18:55:02 +02:00
|
|
|
ramstage-$(CONFIG_VGA_ROM_RUN) += pci_rom.c
|
2009-08-12 17:00:51 +02:00
|
|
|
|