105 lines
3.2 KiB
HTML
105 lines
3.2 KiB
HTML
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<!DOCTYPE html>
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<html>
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<head>
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<title>SoC</title>
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</head>
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<body>
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<h1>x86 System on a Chip (SoC) Development</h1>
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<p>
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SoC development is best done in parallel with development for a specific
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board. The combined steps are listed
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<a target="_blank" href="../x86Development.html">here</a>.
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The development steps for the SoC are listed below:
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</p>
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<ol>
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<li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
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<li>SoC <a href="#RequiredFiles">Required Files</a></li>
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<li><a href="#Descriptor">Start Booting</a></li>
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<li><a href="#EarlyDebug">Early Debug</a></li>
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</ol>
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<hr>
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<h1><a name="RequiredFiles">Required Files</a></h1>
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<p>
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Create the directory as src/soc/<Vendor>/<Chip Family>.
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</p>
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<p>
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The following files are required to build a new SoC:
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</p>
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<ul>
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<li>Include files
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<ul>
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<li>include/soc/pei_data.h</li>
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<li>include/soc/pm.h</li>
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</ul>
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</li>
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<li>Kconfig - Defines the Kconfig value for the SoC and selects the tool
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chains for the various stages:
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<ul>
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<li>select ARCH_BOOTBLOCK_<Tool Chain></li>
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<li>select ARCH_RAMSTAGE_<Tool Chain></li>
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<li>select ARCH_ROMSTAGE_<Tool Chain></li>
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<li>select ARCH_VERSTAGE_<Tool Chain></li>
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</ul>
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</li>
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<li>Makefile.inc - Specify the include paths</li>
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<li>memmap.c - Top of usable RAM</li>
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</ul>
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<hr>
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<h1><a name="Descriptor">Start Booting</a></h1>
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<p>
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Some SoC parts require additional firmware components in the flash.
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This section describes how to add those pieces.
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</p>
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<h2>Intel Firmware Descriptor</h2>
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<p>
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The Intel Firmware Descriptor (IFD) is located at the base of the flash part.
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The following command overwrites the base of the flash image with the Intel
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Firmware Descriptor:
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</p>
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<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre>
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<h2><a name="MEB">Management Engine Binary</a></h2>
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<p>
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Some SoC parts contain and require that the Management Engine (ME) be running
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before it is possible to bring the x86 processor out of reset. A binary file
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containing the management engine code must be added to the firmware using the
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ifdtool. The following commands add this binary blob:
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</p>
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<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom
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mv build/coreboot.rom.new build/coreboot.rom
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</code></pre>
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<h2><a name="EarlyDebug">Early Debug</a></h2>
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<p>
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Early debugging between the reset vector and the time the serial port is enabled
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is most easily done by writing values to port 0x80.
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</p>
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<h2>Success</h2>
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<p>
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When the reset vector is successfully invoked, port 0x80 will output the following value:
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</p>
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<ul>
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<li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
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- Bootblock successfully executed the
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
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and entered the 16-bit code at
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
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</li>
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</ul>
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<hr>
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<p>Modified: 31 January 2016</p>
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</body>
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</html>
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