2020-05-11 23:46:35 +02:00
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Upcoming release - coreboot 4.13
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================================
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The 4.13 release is planned for November 2020.
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Update this document with changes that should be in the release notes.
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* Please use Markdown.
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* See the past few release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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Significant changes
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-------------------
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2020-05-20 18:05:08 +02:00
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### Hidden PCI devices
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This new functionality takes advantage of the existing 'hidden' keyword in the
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devicetree. Since no existing boards were using the keyword, its usage was
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repurposed to make dealing with some unique PCI devices easier. The particular
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case here is Intel's PMC (Power Management Controller). During the FSP-S run,
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the PMC device is made hidden, meaning that its config space looks as if there
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is no device there (Vendor ID reads as 0xFFFF_FFFF). However, the device does
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have fixed resources, both MMIO and I/O. These were previously recorded in
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different places (MMIO was typically an SA fixed resource, and I/O was treated
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as an LPC resource). With this change, when a device in the tree is marked as
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'hidden', it is not probed (`pci_probe_dev()`) but rather assumed to exist so
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that its resources can be placed in a more natural location. This also adds the
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ability for the device to participate in SSDT generation.
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2020-06-05 09:31:21 +02:00
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### Tools for generating SPDs for LP4x memory on TGL and JSL
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A set of new tools `gen_spd.go` and `gen_part_id.go` are added to automate the
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process of generating SPDs for LP4x memory and assigning hardware strap IDs for
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memory parts used on TGL and JSL based boards. The SPD data obtained from memory
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part vendors has to be massaged to format it correctly as per JEDEC and Intel MRC
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expectations. These tools take a list of memory parts describing their physical
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attributes as per their datasheet and convert those attributes into SPD files for
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the platforms. More details about the tools are added in
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[README.md](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/spd_tools/intel/lp4x/README.md).
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2020-05-11 23:46:35 +02:00
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### Add significant changes here
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