39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <intelblocks/xhci.h>
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#define XHCI_USB2_PORT_STATUS_REG 0x480
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#if CONFIG(SOC_INTEL_GLK)
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#define XHCI_USB3_PORT_STATUS_REG 0x510
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#define XHCI_USB2_PORT_NUM 9
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#else
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#define XHCI_USB3_PORT_STATUS_REG 0x500
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#define XHCI_USB2_PORT_NUM 8
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#endif
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#define XHCI_USB3_PORT_NUM 7
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static const struct xhci_usb_info usb_info = {
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.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
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.num_usb2_ports = XHCI_USB2_PORT_NUM,
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.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
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.num_usb3_ports = XHCI_USB3_PORT_NUM,
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};
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const struct xhci_usb_info *soc_get_xhci_usb_info(void)
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{
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return &usb_info;
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}
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