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coreboot-kgpe-d16/src/soc/amd/stoneyridge/Makefile.inc

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soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
#*****************************************************************************
#
# Copyright (c) 2012, 2016-2017 Advanced Micro Devices, Inc.
# 2013 - 2014 Sage Electronic Engineering, LLC
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#*****************************************************************************
soc/amd/stoneyridge: Add CPU files Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-08 00:47:36 +02:00
ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
subdirs-y += ../../../cpu/amd/mtrr/
subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/cache
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/pae
subdirs-y += ../../../cpu/x86/smm
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-26 02:46:46 +02:00
bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
bootblock-y += fixme.c
bootblock-y += bootblock/bootblock.c
bootblock-y += early_setup.c
bootblock-y += tsc_freq.c
romstage-y += romstage.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
romstage-y += early_setup.c
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
romstage-y += dimmSpd.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
soc/amd/stoneyridge: Add CPU files Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-08 00:47:36 +02:00
romstage-y += fixme.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
romstage-y += smbus.c
romstage-y += smbus_spd.c
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
romstage-y += ramtop.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
soc/amd/stoneyridge: Convert monotonic timer Use the TSC for the Stoney Ridge monotonic timer. Modern AMD CPUs have invariant timestamp counters. This patch brings the feature more in line with other devices and allows the use of typical monotonic timer functions. BUG=chrome-os-partner:62578062 Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16 18:10:17 +02:00
romstage-y += tsc_freq.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
ramstage-y += chip.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
soc/amd/stoneyridge: Add CPU files Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-08 00:47:36 +02:00
ramstage-y += fixme.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
ramstage-y += gpio.c
ramstage-y += hda.c
ramstage-y += hudson.c
ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
ramstage-y += lpc.c
soc/amd/stoneyridge: Add CPU files Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-08 00:47:36 +02:00
ramstage-y += model_15_init.c
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
ramstage-y += northbridge.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
ramstage-y += reset.c
ramstage-y += sata.c
ramstage-y += sd.c
ramstage-y += sm.c
ramstage-y += smbus.c
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
ramstage-y += ramtop.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
ramstage-y += usb.c
soc/amd/stoneyridge: Convert monotonic timer Use the TSC for the Stoney Ridge monotonic timer. Modern AMD CPUs have invariant timestamp counters. This patch brings the feature more in line with other devices and allows the use of typical monotonic timer functions. BUG=chrome-os-partner:62578062 Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16 18:10:17 +02:00
ramstage-y += tsc_freq.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
soc/amd/stoneyridge: Convert monotonic timer Use the TSC for the Stoney Ridge monotonic timer. Modern AMD CPUs have invariant timestamp counters. This patch brings the feature more in line with other devices and allows the use of typical monotonic timer functions. BUG=chrome-os-partner:62578062 Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16 18:10:17 +02:00
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi
# ROMSIG At ROMBASE + 0x20000:
# +-----------+---------------+----------------+------------+
# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
# +-----------+---------------+----------------+------------+
# |PSPDIR ADDR|
# +-----------+
#
# EC ROM should be 64K aligned.
STONEYRIDGE_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1)
### 0
FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))
FIRMWARE_TYPE=ST
###5
CONFIG_PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key
###1
CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin
###3
CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin
###2
CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin
###4
CONFIG_PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin
###8
CONFIG_SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin
CONFIG_SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin
###95
CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin
###9
CONFIG_PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key
###12
CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin
###13
CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin
###18
CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin
CONFIG_SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin
add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci)
OPT_STONEYRIDGE_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_IMC_FWM_FILE), --imc)
OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILEddd), --gec)
CONFIG_2AMD_PUBKEY_FILE =$(CONFIG_AMD_PUBKEY_FILE)
CONFIG_2PSPBTLDR_FILE =$(CONFIG_PSPBTLDR_FILE)
CONFIG_2SMUFWM_FILE =$(CONFIG_SMUFWM_FILE)
CONFIG_2SMUFWM_FN_FILE =$(CONFIG_SMUFWM_FN_FILE)
CONFIG_2PSPRCVR_FILE =$(CONFIG_PSPRCVR_FILE)
CONFIG_2PUBSIGNEDKEY_FILE =$(CONFIG_PUBSIGNEDKEY_FILE)
CONFIG_2PSPSCUREOS_FILE =$(CONFIG_PSPSCUREOS_FILE)
CONFIG_2PSPNVRAM_FILE =$(CONFIG_PSPNVRAM_FILE)
CONFIG_2PSPSECUREDEBUG_FILE =$(CONFIG_PSPSECUREDEBUG_FILE)
CONFIG_2PSPTRUSTLETS_FILE =$(CONFIG_PSPTRUSTLETS_FILE)
CONFIG_2TRUSTLETKEY_FILE =$(CONFIG_TRUSTLETKEY_FILE)
CONFIG_2SMUFIRMWARE2_FILE =$(CONFIG_SMUFIRMWARE2_FILE)
CONFIG_2SMUFIRMWARE2_FN_FILE =$(CONFIG_SMUFIRMWARE2_FN_FILE)
CONFIG_2SMUSCS_FILE =$(CONFIG_SMUSCS_FILE)
OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_2AMD_PUBKEY_FILE), --pubkey2)
OPT_2PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPBTLDR_FILE), --bootloader2)
OPT_2SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FILE), --smufirmware_2)
OPT_2PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPRCVR_FILE), --recovery2)
OPT_2PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_2PUBSIGNEDKEY_FILE), --rtmpubkey2)
OPT_2PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_2PSPSCUREOS_FILE), --secureos2)
OPT_2PSPNVRAM_FILE=$(call add_opt_prefix, $(CONFIG_2PSPNVRAM_FILE), --nvram2)
OPT_2PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(CONFIG_2PSPSECUREDEBUG_FILE), --securedebug2)
OPT_2PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(CONFIG_2PSPTRUSTLETS_FILE), --trustlets2)
OPT_2TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_2TRUSTLETKEY_FILE), --trustletkey2)
OPT_2SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFIRMWARE2_FILE), --smufirmware2_2)
OPT_2SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_2SMUSCS_FILE), --smuscs2)
OPT_2SMUFWM_FN_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FN_FILE), --smufnfirmware_2)
OPT_2SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFIRMWARE2_FN_FILE), --smufnfirmware2_2)
$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \
$(call strip_quotes, $(CONFIG_STONEYRIDGE_IMC_FWM_FILE)) \
$(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \
$(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
$(call strip_quotes, $(CONFIG_PUBSIGNEDKEY_FILE)) \
$(call strip_quotes, $(CONFIG_PSPBTLDR_FILE)) \
$(call strip_quotes, $(CONFIG_PSPRCVR_FILE)) \
$(call strip_quotes, $(CONFIG_PSPSCUREOS_FILE)) \
$(call strip_quotes, $(CONFIG_PSPNVRAM_FILE)) \
$(call strip_quotes, $(CONFIG_SMUFWM_FILE)) \
$(call strip_quotes, $(CONFIG_SMUSCS_FILE)) \
$(call strip_quotes, $(CONFIG_PSPSECUREDEBUG_FILE)) \
$(call strip_quotes, $(CONFIG_PSPTRUSTLETS_FILE)) \
$(call strip_quotes, $(CONFIG_TRUSTLETKEY_FILE)) \
$(call strip_quotes, $(CONFIG_SMUFIRMWARE2_FILE)) \
$(call strip_quotes, $(CONFIG_2AMD_PUBKEY_FILE)) \
$(call strip_quotes, $(CONFIG_2PUBSIGNEDKEY_FILE)) \
$(call strip_quotes, $(CONFIG_2PSPBTLDR_FILE)) \
$(call strip_quotes, $(CONFIG_2SMUFWM_FILE)) \
$(call strip_quotes, $(CONFIG_2SMUFWM_FN_FILE)) \
$(call strip_quotes, $(CONFIG_2PSPRCVR_FILE)) \
$(call strip_quotes, $(CONFIG_2PSPSCUREOS_FILE)) \
$(call strip_quotes, $(CONFIG_2PSPNVRAM_FILE)) \
$(call strip_quotes, $(CONFIG_2SMUSCS_FILE)) \
$(call strip_quotes, $(CONFIG_2PSPSECUREDEBUG_FILE)) \
$(call strip_quotes, $(CONFIG_2PSPTRUSTLETS_FILE)) \
$(call strip_quotes, $(CONFIG_2TRUSTLETKEY_FILE)) \
$(call strip_quotes, $(CONFIG_2SMUFIRMWARE2_FILE)) \
$(call strip_quotes, $(CONFIG_2SMUFIRMWARE2_FN_FILE)) \
$(AMDFWTOOL)
rm -f $@
@printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
$(AMDFWTOOL) \
$(OPT_STONEYRIDGE_XHCI_FWM_FILE) \
$(OPT_STONEYRIDGE_IMC_FWM_FILE) \
$(OPT_STONEYRIDGE_GEC_FWM_FILE) \
$(OPT_AMD_PUBKEY_FILE) \
$(OPT_PSPBTLDR_FILE) \
$(OPT_SMUFWM_FILE) \
$(OPT_PSPRCVR_FILE) \
$(OPT_PUBSIGNEDKEY_FILE) \
$(OPT_PSPSCUREOS_FILE) \
$(OPT_PSPNVRAM_FILE) \
$(OPT_PSPSECUREDEBUG_FILE) \
$(OPT_PSPTRUSTLETS_FILE) \
$(OPT_TRUSTLETKEY_FILE) \
$(OPT_SMUFIRMWARE2_FILE) \
$(OPT_SMUSCS_FILE) \
$(OPT_2AMD_PUBKEY_FILE) \
$(OPT_2PSPBTLDR_FILE) \
$(OPT_2SMUFWM_FILE) \
$(OPT_2SMUFWM_FN_FILE) \
$(OPT_2PSPRCVR_FILE) \
$(OPT_2PUBSIGNEDKEY_FILE) \
$(OPT_2PSPSCUREOS_FILE) \
$(OPT_2PSPNVRAM_FILE) \
$(OPT_2PSPSECUREDEBUG_FILE) \
$(OPT_2PSPTRUSTLETS_FILE) \
$(OPT_2TRUSTLETKEY_FILE) \
$(OPT_2SMUFIRMWARE2_FILE) \
$(OPT_2SMUFIRMWARE2_FN_FILE) \
$(OPT_2SMUSCS_FILE) \
--flashsize $(CONFIG_ROM_SIZE) \
--output $@
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
PHONY+=add_amdfw
INTERMEDIATE+=add_amdfw
add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom
printf " DD Adding AMD Firmware\n"
dd if=$(obj)/amdfw.rom \
of=$(obj)/coreboot.pre conv=notrunc bs=1 seek=131072 >/dev/null 2>&1
else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
cbfs-files-y += apu/amdfw
apu/amdfw-file := $(obj)/amdfw.rom
apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION)
apu/amdfw-type := raw
endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
soc/amd/stoneyridge: Add CPU files Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-08 00:47:36 +02:00
endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
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