2014-08-25 07:47:20 +02:00
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/*
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*
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* Copyright 2014 Google Inc.
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* Copyright (C) 2003-2004 Olivier Houchard
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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2022-05-15 23:42:57 +02:00
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#ifndef __ARCH_BARRIER_H__
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2014-08-25 07:47:20 +02:00
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#define __ARCH_BARRIER_H__
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#include <arch/cache.h>
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/*
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* Description of different memory barriers introduced:
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*
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* Memory barrier(mb) - Guarantees that all memory accesses specified before the
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* barrier will happen before all memory accesses specified after the barrier
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*
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* Read memory barrier (rmb) - Guarantees that all read memory accesses
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* specified before the barrier will happen before all read memory accesses
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* specified after the barrier
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*
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* Write memory barrier (wmb) - Guarantees that all write memory accesses
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* specified before the barrier will happen before all write memory accesses
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* specified after the barrier
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*/
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/*
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* According to ARM Reference Manual (ARMv7-A), by default dmb ensures:
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* Full system is the required shareability domain
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* Reads and writes are the required access types.
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*/
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#define mb() dmb()
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#define rmb() dmb()
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#define wmb() dmb()
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#endif /* __ARCH_BARRIER_H__ */
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