GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
coreboot-kgpe-d16/util/crossgcc/patches/gcc-5.3.0_nds32.patch

18 lines
649 B
Diff
Raw Normal View History

crossgcc: Update toolchain New tools: * mpfr 3.1.4 * binutils 2.26 * gcc 5.3.0 * llvm/clang 3.8.0 Patch changes: * binutils-2.25_fix-aarch64.patch: fixed in 2.26 * binutils-2.25_host-clang.patch: the positions of header file includes have been adjusted * binutils-2.25_no-bfd-doc.patch: update to 2.26 * binutils-2.25_riscv.patch: update from riscv-gnu-toolchain * gcc-5.2.0_elf_biarch.patch: update to 5.3.0 * gcc-5.2.0_gnat.patch: update to 5.3.0 * gcc-5.2.0_libgcc.patch: update to 5.3.0 * gcc-5.2.0_nds32.patch: update to 5.3.0 * gcc-5.2.0_riscv.patch: update from riscv-gnu-toolchain * cfe-3.7.1.src_frontend.patch: update to 3.8.0 In the latest code of riscv-gnu-toolchain project, the patch for {binutils,gcc}/config.sub has been removed, and the target is renamed as riscv32 and riscv64. The `riscv' to `riscv64' change in xcompile is in another commit. Test results: All GCC and LLVM/clang toolchain build successfully. x86,arm: qemu boots power8: firmware fails to boot aarch64,mips: not tested riscv: firmware fails to build with new binutils clang: firmware fails to boot Signed-off-by: Iru Cai <mytbk920423@gmail.com> Change-Id: I42ce89c29263d768d161c28199994f17d0389633 Reviewed-on: https://review.coreboot.org/14227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-02 04:50:59 +02:00
diff -urN gcc-5.3.0.orig/gcc/config/nds32/nds32.md gcc-5.3.0/gcc/config/nds32/nds32.md
--- gcc-5.3.0.orig/gcc/config/nds32/nds32.md 2015-01-15 22:45:09.000000000 -0800
+++ gcc-5.3.0/gcc/config/nds32/nds32.md 2016-04-14 22:09:09.000000000 -0700
crossgcc: Fix out of bounds array access for nds32le Patch from Segher Boessenkool <segher@kernel.crashing.org> Change-Id: Ia91e0d6e50399da38afd8cdc0b92c82e4efa0a08 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14380 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-15 19:12:57 +02:00
@@ -2289,11 +2289,11 @@
emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
operands[4]));
- operands[5] = gen_reg_rtx (SImode);
+ rtx tmp = gen_reg_rtx (SImode);
/* Step C, D, E, and F, using another temporary register operands[5]. */
emit_jump_insn (gen_casesi_internal (operands[0],
operands[3],
- operands[5]));
+ tmp));
DONE;
})