33 lines
994 B
C
33 lines
994 B
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _SOC_APOLLOLAKE_CHIP_H_
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#define _SOC_APOLLOLAKE_CHIP_H_
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#define CLKREQ_DISABLED 0xf
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struct soc_intel_apollolake_config {
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/*
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* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
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* four CLKREQ inputs, but six root ports. Root ports without an
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* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
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*/
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uint8_t pcie_rp0_clkreq_pin;
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uint8_t pcie_rp1_clkreq_pin;
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uint8_t pcie_rp2_clkreq_pin;
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uint8_t pcie_rp3_clkreq_pin;
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uint8_t pcie_rp4_clkreq_pin;
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uint8_t pcie_rp5_clkreq_pin;
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};
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#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
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