34 lines
822 B
C
34 lines
822 B
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <arch/cpu.h>
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#include <program_loading.h>
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#include <soc/cpu.h>
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/*
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* This file supports the necessary hoops one needs to jump through since
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* early FSP component and early stages are running from cache-as-ram.
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*/
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static void flush_l1d_to_l2(void)
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{
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msr_t msr = rdmsr(MSR_POWER_MISC);
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msr.lo |= (1 << 8);
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wrmsr(MSR_POWER_MISC, msr);
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}
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void platform_prog_run(struct prog *prog)
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{
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/* Flush L1D cache to L2 */
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flush_l1d_to_l2();
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}
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