31 lines
971 B
C
31 lines
971 B
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <fsp/api.h>
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#include <soc/ramstage.h>
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/* UPD parameters to be initialized before SiliconInit */
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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/* ToDo: update with UPD override as FSP matures */
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}
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/* Mainboard GPIO Configuration */
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__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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