GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
coreboot-kgpe-d16/src/soc/intel/skylake/acpi/serialio.asl

103 lines
2.1 KiB
Text
Raw Normal View History

soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
/*
* This file is part of the coreboot project.
*
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
* Copyright (C) 2015 Google Inc.
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
* Copyright (C) 2015 Intel Corporation.
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
/* Intel Serial IO Devices */
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Device (I2C0)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
Name (_ADR, 0x00150000)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO I2C Controller 0")
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
}
Device (I2C1)
{
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
Name (_ADR, 0x00150001)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO I2C Controller 1")
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (SSCN, Package () { 528, 640, 30 })
Name (FMCN, Package () { 128, 160, 30 })
Name (FPCN, Package () { 48, 64, 30})
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Device (I2C2)
{
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
Name (_ADR, 0x00150002)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO I2C Controller 2")
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Device (I2C3)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
Name (_ADR, 0x00150003)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO I2C Controller 3")
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Device (I2C4)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (_ADR, 0x00190002)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO I2C Controller 4")
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Device (I2C5)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (_ADR, 0x00190002)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO I2C Controller 5")
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Device (SPI0)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (_ADR, 0x001E0002)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO SPI Controller 0")
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Device (SPI1)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Name (_ADR, 0x001E0003)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO SPI Controller 1")
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
}
Device (UAR0)
{
Name (_ADR, 0x001E0000)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO UART Controller 0")
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
}
Device (UAR1)
{
Name (_ADR, 0x001E0001)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO UART Controller 1")
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
Device (UAR2)
{
Name (_ADR, 0x00190000)
skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 01:58:23 +02:00
Name (_DDN, "Serial IO UART Controller 2")
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
}
Reference in a new issue Copy permalink