52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2015, NVIDIA CORPORATION.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/clk_rst.h>
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#include <soc/clock.h>
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#include <soc/padconfig.h>
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#include <soc/power.h>
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static void enable_ape_periph_clocks(void)
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{
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clock_enable(0, 0, 0, CLK_V_APB2APE, 0, 0, CLK_Y_APE);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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}
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static void unreset_ape_periphs(void)
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{
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clock_clr_reset(0, 0, 0, CLK_V_APB2APE, 0, 0, CLK_Y_APE);
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}
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/*
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* Audio on Tegra210 requires some special init.
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* The APE block must be unpowergated, and a couple of
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* audio-based peripherals must be clocked and taken
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* out of reset so that I2S/AXBAR/APB2APE registers can
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* be configured to enable audio flow.
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*/
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void soc_configure_ape(void)
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{
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power_ungate_partition(POWER_PARTID_APE);
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enable_ape_periph_clocks();
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remove_clamps(POWER_PARTID_APE);
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unreset_ape_periphs();
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}
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