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spd/lp5: Generate initial SPDs for Sabrina SoC Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02 06:29:57 +01:00
# Generated by:
spd/lp5: Add new part H58G56BK8BX068 HYNIX H58G56BK8BX068 will be used for omnigul. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:264340545 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Id4adbaf7611e34107522df988482d9efd229d514 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72967 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-13 03:26:57 +01:00
# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
spd/lp5: Generate initial SPDs for Sabrina SoC Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02 06:29:57 +01:00
MT62F512M32D2DR-031 WT:B,spd-1.hex
MT62F1G32D4DR-031 WT:B,spd-2.hex
H9JCNNNCP3MLYR-N6E,spd-2.hex
K3LKBKB0BM-MGCP,spd-3.hex
spd/lp5: Add new part H9JCNNNBK3MLYR-N6E Hynix H9JCNNNBK3MLYR-N6E will be used for nereid P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:217096008 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I8775fe0551e0712507d42a778e04745a07270d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-13 23:57:37 +01:00
H9JCNNNBK3MLYR-N6E,spd-1.hex
spd/lp5: Add new part MT62F2G32D8DR-031 Micron MT62F2G32D8DR-031 will be used for skyrim P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:213926260 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62542 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 16:50:39 +01:00
MT62F2G32D8DR-031 WT:B,spd-4.hex
util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina Firmware component that does memory training already limits the memory controller to train at 5500 Mbps for all memory parts in Sabrina. Hence removing this interim SPD change to limit the speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-30 01:19:48 +02:00
K3LKLKL0EM-MGCN,spd-5.hex
spd/lp5: Add new LP5 part H58G56AK6BX069 Hynix H58G56AK6BX069 will be used by the brya variant crota. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:233830713 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I6136e17706c6248598886f8f9bd8fdd7efff4dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/64662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-01 03:35:57 +02:00
H58G56AK6BX069,spd-3.hex
mb/google/skyrim/var/winterhold: Update Lp5x and Lp5 memory support Update K3KL8L80CM-MGCT, K3KL9L90CM-MGCT,H58G66AK6BX070 support BRANCH=None BUG=b:243337816 TEST= SPD add Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2c370fbd007c22b1f94074d9f16e5bc7c4e04848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-26 17:02:57 +02:00
H58G66AK6BX070,spd-6.hex
spd/lp5: Add SPD for Micron MT62F1G32D4DS This adds support for Micron "MT62F1G32D4DS-031 WT:B" LP5 chips. generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=none BUG=b:233822309 Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-01 04:55:28 +02:00
MT62F1G32D4DS-031 WT:B,spd-2.hex
util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina Firmware component that does memory training already limits the memory controller to train at 5500 Mbps for all memory parts in Sabrina. Hence removing this interim SPD change to limit the speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-30 01:19:48 +02:00
K3LKCKC0BM-MGCP,spd-6.hex
MT62F1G32D2DS-026 WT:B,spd-7.hex
MT62F2G32D4DS-026 WT:B,spd-8.hex
spd/lp5: Add SPD for Samsung K3KL6L60GM-MGCT This adds support for Samsung K3KL6L60GM-MGCT chips. BUG=b:270708359 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I64b2623bc8da94c1fd3a935ec5368cdc6e76505b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-01 11:52:14 +01:00
K3KL6L60GM-MGCT,spd-9.hex
mb/google/skyrim/var/winterhold: Update Lp5x and Lp5 memory support Update K3KL8L80CM-MGCT, K3KL9L90CM-MGCT,H58G66AK6BX070 support BRANCH=None BUG=b:243337816 TEST= SPD add Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2c370fbd007c22b1f94074d9f16e5bc7c4e04848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-26 17:02:57 +02:00
K3KL8L80CM-MGCT,spd-7.hex
K3KL9L90CM-MGCT,spd-8.hex
spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068 Add Hynix H58G66BK7BX067 and H58G56BK7BX068 in the memory_parts.json and re-generate the SPD. BUG=b:243337816 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I8d6aac3ecec36b126e7e41d6c9475695aa7a26b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-07 10:47:22 +02:00
H58G66BK7BX067,spd-8.hex
H58G56BK7BX068,spd-7.hex
spd/lp5: Update memory configuration of H9JCNNNFA5MLYR-N6E Update bitWidthPerChannel in memory_parts.json and re-generate the SPD. Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E. BUG=b:261530632 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 03:03:50 +01:00
H9JCNNNFA5MLYR-N6E,spd-4.hex
spd/lp5: Modify Hynix LPDDR5X memory Speed Because SPD tool now supports 8533Mbps, so modify speed to regenerate the SPD file for Hynix H58G66BK8BX067 and H58G56BK8BX068. BUG=b:263189532, b:270629852 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73251 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-02-24 07:35:44 +01:00
H58G66BK8BX067,spd-10.hex
H58G56BK8BX068,spd-11.hex
spd/lp5: Add 2 Micron memory parts Add Micron memory part MT62F1G32D2DS-023 and MT62F2G32D4DS-023 to LP5 global list. Attributes are derived from CCM005-1974498342-145. Also, regenerate the SPD files for the SoC. BUG=b:271188237 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: I6675a68b7a515bd6d21db3ea2da762b06dee017a Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-06 09:44:58 +01:00
MT62F1G32D2DS-023 WT:B,spd-11.hex
MT62F2G32D4DS-023 WT:B,spd-10.hex