coreboot-kgpe-d16/spd/lp5/platforms_manifest.generate...

# Generated by:
# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

ADL,set-0
MTL,set-0
SBR,set-1
spd: Add lp5 directory with empty memory_parts file Add spd/lp5/memory_parts.json with an empty parts list, then run spd_gen to generate the manifests and empty SPD. Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: I0314314130a1ccc58fb5a0416b110e7a86338fd0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> 2021-11-03 23:55:07 +01:00			`# Generated by:`
			`# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5`

			`ADL,set-0`
util/spd_tools: Add Intel Meteor Lake (MTL) platform This patch add support for MTL platform to the `spd_tools`. This would be useful to create dynamic SPD for rex variants. BUG=b:224325352 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1db6e3a63d2842c12ef0f256ba1d32b9258670f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> 2022-06-28 12:13:00 +02:00			`MTL,set-0`
spd/lp5: Generate initial SPDs for Sabrina SoC Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> 2022-02-02 06:29:57 +01:00			`SBR,set-1`