2017-11-28 00:38:53 +01:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Maxim MAX98373 audio codec devicetree bindings
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*/
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struct drivers_i2c_max98373_config {
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/* I2C Bus Frequency in Hertz (default 400kHz) */
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uint32_t bus_speed;
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2018-05-21 01:46:51 +02:00
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/* Set '1' if I2S channel size is not 32bit. */
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2017-11-28 00:38:53 +01:00
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bool interleave_mode;
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/* Identifier for chips */
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uint32_t uid;
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/* Device Description */
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const char *desc;
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/* ACPI Device Name */
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const char *name;
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/* slot number where voltage feedback will be received */
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uint32_t vmon_slot_no;
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/* slot number where current feedback will be received */
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uint32_t imon_slot_no;
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};
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