2015-05-06 00:07:29 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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2015-04-21 00:20:28 +02:00
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* Copyright (C) 2015 Intel Corp.
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2015-05-06 00:07:29 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/iosf.h>
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#include <soc/nvs.h>
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#include <soc/ramstage.h>
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void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
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{
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struct resource *bar;
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global_nvs_t *gnvs;
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2015-04-21 00:20:28 +02:00
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printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x )\n",
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__FILE__, __func__, dev_name(dev), iosf_reg, nvs_index);
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2015-05-06 00:07:29 +02:00
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/* Find ACPI NVS to update BARs */
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2015-04-21 00:20:28 +02:00
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gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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2015-05-06 00:07:29 +02:00
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if (!gnvs) {
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printk(BIOS_ERR, "Unable to locate Global NVS\n");
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return;
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}
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/* Save BAR0 and BAR1 to ACPI NVS */
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bar = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (bar)
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gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base;
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/* Device is enabled in ACPI mode */
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gnvs->dev.scc_en[nvs_index] = 1;
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}
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