2010-02-19 20:59:03 +01:00
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/*
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2010-04-13 15:43:35 +02:00
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* This file is part of the coreboot project.
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2010-02-19 20:59:03 +01:00
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*
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2010-04-13 15:43:35 +02:00
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* Copyright (C) 2006 Advanced Micro Devices, Inc.
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* Copyright (C) 2008-2010 coresystems GmbH
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2015-09-04 19:06:05 +02:00
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* Copyright 2015 Google Inc
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2010-04-13 15:43:35 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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2010-02-19 20:59:03 +01:00
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*
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2010-04-13 15:43:35 +02:00
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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2010-02-19 20:59:03 +01:00
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*/
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2015-09-05 20:31:14 +02:00
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/* This file is included inside a SECTIONS block */
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. = CONFIG_DCACHE_RAM_BASE;
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.car.data . (NOLOAD) : {
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2015-09-29 23:31:20 +02:00
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/* Vboot work buffer is completely volatile outside of verstage and
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* romstage. Appropriate code needs to handle the transition. */
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#if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)
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VBOOT2_WORK(., 16K)
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2016-02-09 02:17:05 +01:00
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#endif
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/* Stack for CAR stages. Since it persists across all stages that
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* use CAR it can be reused. The chipset/SoC is expected to provide
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* the stack size. */
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#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
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_car_stack_start = .;
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. += CONFIG_DCACHE_BSP_STACK_SIZE;
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_car_stack_end = .;
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2015-09-29 23:31:20 +02:00
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#endif
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2015-09-24 19:18:07 +02:00
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/* The pre-ram cbmem console as well as the timestamp region are fixed
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* in size. Therefore place them at the beginning .car.data section
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* so that multiple stages (romstage and verstage) have a consistent
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* link address of these shared objects. */
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PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
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2015-09-05 20:31:14 +02:00
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_car_data_start = .;
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2015-09-24 19:18:07 +02:00
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/* The timestamp implementation relies on this storage to be around
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* after migration. One of the fields indicates not to use it as the
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* backing store once cbmem comes online. Therefore, this data needs
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* to reside in the migrated area (between _car_data_start and
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* _car_data_end). */
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2015-09-05 20:31:14 +02:00
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TIMESTAMP(., 0x100)
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2015-09-24 19:18:07 +02:00
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/* _car_global_start and _car_global_end provide symbols to per-stage
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* variables that are not shared like the timestamp and the pre-ram
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* cbmem console. This is useful for clearing this area on a per-stage
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* basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
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_car_global_start = .;
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2015-09-05 20:31:14 +02:00
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*(.car.global_data);
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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2015-09-24 19:18:07 +02:00
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_car_global_end = .;
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2015-09-05 20:31:14 +02:00
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_car_data_end = .;
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}
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2011-10-01 13:27:32 +02:00
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2015-09-05 20:31:14 +02:00
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/* Global variables are not allowed in romstage
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* This section is checked during stage creation to ensure
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* that there are no global variables present
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*/
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2014-10-30 19:53:38 +01:00
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2015-09-05 20:31:14 +02:00
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. = 0xffffff00;
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.illegal_globals . : {
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2016-01-23 01:24:33 +01:00
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
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2015-09-05 20:31:14 +02:00
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*(.bss)
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*(.bss.*)
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*(.sbss)
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*(.sbss.*)
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2010-02-19 20:59:03 +01:00
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}
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2015-09-05 20:31:14 +02:00
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2015-09-24 19:18:07 +02:00
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_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
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