83 lines
2.1 KiB
HTML
83 lines
2.1 KiB
HTML
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<!DOCTYPE html>
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<html>
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<head>
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<title>Board</title>
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</head>
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<body>
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<h1>x86 Board Development</h1>
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<p>
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Board development requires System-on-a-Chip (SoC) support.
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The combined steps are listed
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<a target="_blank" href="../x86Development.html">here</a>.
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The development steps for the board are listed below:
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</p>
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<ol>
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<li><a href="#RequiredFiles">Required Files</a></li>
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</ol>
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<hr>
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<h1><a name="RequiredFiles">Required Files</a></h1>
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<p>
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Create the board directory as src/mainboard/<Vendor>/<Board>.
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</p>
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<p>
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The following files are required to build a new board:
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</p>
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<ol>
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<li>Kconfig.name - Defines the Kconfig value for the board</li>
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<li>Kconfig
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<ol type="A">
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<li>Selects the SoC for the board and specifies the SPI flash size
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<ol type="I">
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<li>BOARD_ROMSIZE_KB_<Size></li>
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<li>SOC_<Vendor>_<Chip Family></li>
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</ol>
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</li>
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<li>Declare the Kconfig values for:
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<ol type="I">
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<li>MAINBOARD_DIR</li>
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<li>MAINBOARD_PART_NUMBER</li>
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<li>MAINBOARD_VENDOR</li>
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</ol>
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</li>
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</ol>
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</li>
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<li>devicetree.cb - Enable root bridge and serial port
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<ol type="A">
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<li>The first line must be "chip soc/Intel/<soc family>";
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this path is used by the generated static.c to include the chip.h
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header file
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</li>
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</ol>
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</li>
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<li>romstage.c
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<ol type="A">
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<li>Add routine mainboard_romstage_entry which calls romstage_common</li>
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</ol>
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</li>
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<li>Configure coreboot build:
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<ol type="A">
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<li>Set LOCALVERSION</li>
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<li>FLASHMAP_OFFSET = 0x00700000</li>
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<li>Select vendor for the board</li>
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<li>Select the board</li>
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<li>CBFS_SIZE = 0x00100000</li>
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<li>Set the CPU_MICROCODE_CBFS_LEN</li>
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<li>Set the CPU_MICROCODE_CBFS_LOC</li>
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<li>Set the FSP_IMAGE_ID_STRING</li>
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<li>Set the FSP_LOC</li>
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<li>Disable GOP_SUPPORT</li>
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<li>No payload</li>
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<li>Choose the default value for all other options</li>
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</ol>
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</li>
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</ol>
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<hr>
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<p>Modified: 31 January 2016</p>
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</body>
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</html>
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