43 lines
1.5 KiB
C
43 lines
1.5 KiB
C
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/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <delay.h>
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#include <arch/io.h>
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#include <soc.h>
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#include <clk_rst.h>
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#include <clock.h>
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static struct clk_rst_ctlr *clk_rst = (void *)NV_PA_CLK_RST_BASE;
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/*
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* On poweron, AVP clock source (also called system clock) is set to PLLP_out0
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* with frequency set at 1MHz. Before initializing PLLP, we need to move the
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* system clock's source to CLK_M temporarily. And then switch it to PLLP_out4
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* (204MHz) at a later time.
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*/
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void set_avp_clock_to_clkm(void)
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{
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u32 val;
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val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
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(SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
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(SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
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(SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
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(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
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writel(val, &clk_rst->crc_sclk_brst_pol);
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/* Wait 2-3us for the clock to flush thru the logic as per the TRM */
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udelay(3);
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}
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