coreboot-kgpe-d16/src/soc/intel/Kconfig

source src/soc/intel/baytrail/Kconfig
source src/soc/intel/broadwell/Kconfig
source src/soc/intel/fsp_baytrail/Kconfig
source src/soc/intel/common/Kconfig
baytrail: add initial support The initial Bay Trail code is intended to support the mobile and desktop version of Bay Trail. This support can train memory and execute through ramstage. However, the resource allocation is not curently handled correctly. The MRC cache parameters are successfully saved and reused after the initial cold boot. BUG=chrome-os-partner:22292 BRANCH=None TEST=Built and booted on a reference board through ramstage. Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168387 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4847 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> 2013-09-07 07:41:48 +02:00			`source src/soc/intel/baytrail/Kconfig`
broadwell: Hook into the build system Hook the soc/intel/broadwell directory into the configuration and build system so it can be used by mainboards. BUG=chrome-os-partner:28234 TEST=build and boot on wtm2 Original-Change-Id: Ia48ac644a8cefb2cf9c64efaa1bd9737ddfb8b1f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ee290d7f6e541999e077bcf871cd6c7b6504f3d6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iea5f37a839b516ac98227cc1737ce0d03f7e7e3b Reviewed-on: http://review.coreboot.org/7940 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> 2014-05-14 23:13:42 +02:00			`source src/soc/intel/broadwell/Kconfig`
fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip While similar to the Bay Trail-M/D code based on the MRC, there are many differences as well: - Obviously, uses the FSP instead of the MRC binaries. - FSP does additional hardware setup, so coreboot doesn't need to. - Different microcode & microcode loading method - Uses the cache_as_ram.inc from the FSP Driver - Various other changes in support of the FSP Additional changes that don't have to to with the FSP vs MRC: - Updated IRQ Routing - Different FADT implementation. This was validated with FSP: BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5 MD5: 9360cd915f0d3e4116bbc782233d7b91 Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5791 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> 2014-05-13 05:55:00 +02:00			`source src/soc/intel/fsp_baytrail/Kconfig`
baytrail: Move MRC cache code to a common directory This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> 2014-04-22 19:46:06 +02:00			`source src/soc/intel/common/Kconfig`