coreboot-kgpe-d16/src/cpu/intel/haswell/Kconfig


config CPU_INTEL_HASWELL
	bool

if CPU_INTEL_HASWELL

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select SMP
	select SSE2
	select UDELAY_LAPIC
	select SMM_TSEG
	select CPU_MICROCODE_IN_CBFS
	#select AP_IN_SIPI_WAIT
	select TSC_SYNC_MFENCE
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE

config BOOTBLOCK_CPU_INIT
	string
	default "cpu/intel/haswell/bootblock.c"

config SERIAL_CPU_INIT
	bool
	default n

config SMM_TSEG_SIZE
	hex
	default 0x800000

config MICROCODE_INCLUDE_PATH
	string
	default "src/cpu/intel/haswell"

endif
haswell: Add initial support for Haswell platforms The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> 2012-10-30 15:03:43 +01:00
			`config CPU_INTEL_HASWELL`
			`bool`

			`if CPU_INTEL_HASWELL`

			`config CPU_SPECIFIC_OPTIONS`
			`def_bool y`
			`select SMP`
			`select SSE2`
			`select UDELAY_LAPIC`
			`select SMM_TSEG`
			`select CPU_MICROCODE_IN_CBFS`
			`#select AP_IN_SIPI_WAIT`
			`select TSC_SYNC_MFENCE`
x86 intel: Add Firmware Interface Table support Haswell CPUs require a FIT table in the firmware. This commit adds rudimentary support for a FIT table. The number of entries in the table is based on a configuration option. The code only generates a type 0 entry. A follow-on tool will need to be developed to populate the FIT entries as well as checksumming the table. Verified image has a FIT pointer and table when option is selected. Change-Id: I3a314016a09a1cc26bf1fb5d17aa50853d2ef4f8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> 2012-12-03 23:17:40 +01:00			`select CPU_INTEL_FIRMWARE_INTERFACE_TABLE`
haswell: Add initial support for Haswell platforms The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> 2012-10-30 15:03:43 +01:00
			`config BOOTBLOCK_CPU_INIT`
			`string`
			`default "cpu/intel/haswell/bootblock.c"`

			`config SERIAL_CPU_INIT`
			`bool`
			`default n`

			`config SMM_TSEG_SIZE`
			`hex`
			`default 0x800000`

			`config MICROCODE_INCLUDE_PATH`
			`string`
			`default "src/cpu/intel/haswell"`

			`endif`