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coreboot-kgpe-d16/src/mainboard/asus/a8v-e_deluxe/dsdt.asl

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Add a target for the ASUS A8V-E Deluxe (trivial). For now this is a plain copy of the ASUS A8V-E SE target, I reported that most of the code also works (sort of) for the ASUS A8V-E Deluxe a long while ago, see http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html http://www.coreboot.org/ASUS_A8V-E_Deluxe There will be a bunch of changes necessary though (devicetree.cb, mptable.c, ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target. Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as otherwise there will be build errors if the MAINBOARD_PART_NUMBER string gets too long (as is the case for "A8V-E Deluxe"). The error is: ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps section .romstrap loaded at [00000000ffffff80,00000000ffffffd3] (both with stock Debian gcc and with xgcc) Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
Remove address from GPLv2 headers As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-03-26 15:17:45 +01:00
* Foundation, Inc.
Add a target for the ASUS A8V-E Deluxe (trivial). For now this is a plain copy of the ASUS A8V-E SE target, I reported that most of the code also works (sort of) for the ASUS A8V-E Deluxe a long while ago, see http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html http://www.coreboot.org/ASUS_A8V-E_Deluxe There will be a bunch of changes necessary though (devicetree.cb, mptable.c, ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target. Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as otherwise there will be build errors if the MAINBOARD_PART_NUMBER string gets too long (as is the case for "A8V-E Deluxe"). The error is: ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps section .romstrap loaded at [00000000ffffff80,00000000ffffffd3] (both with stock Debian gcc and with xgcc) Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 22:48:14 +01:00
*/
/*
* ISA portions taken from QEMU acpi-dsdt.dsl.
*/
Use ACPI text fields consistently with all other boards LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 Reviewed-on: http://review.coreboot.org/224 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-20 22:36:32 +02:00
DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
Add a target for the ASUS A8V-E Deluxe (trivial). For now this is a plain copy of the ASUS A8V-E SE target, I reported that most of the code also works (sort of) for the ASUS A8V-E Deluxe a long while ago, see http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html http://www.coreboot.org/ASUS_A8V-E_Deluxe There will be a bunch of changes necessary though (devicetree.cb, mptable.c, ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target. Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as otherwise there will be build errors if the MAINBOARD_PART_NUMBER string gets too long (as is the case for "A8V-E Deluxe"). The error is: ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps section .romstrap loaded at [00000000ffffff80,00000000ffffffd3] (both with stock Debian gcc and with xgcc) Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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{
/* For now only define 2 power states:
* - S0 which is fully on
* - S5 which is soft off
* Any others would involve declaring the wake up methods.
*/
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
/* Root of the bus hierarchy */
Scope (\_SB)
{
/* Top PCI device */
Device (PCI0)
{
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00)
Name (_UID, 0x00)
Name (_BBN, 0x00)
/* PCI Routing Table */
/* aaa */
Name (_PRT, Package () {
Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
})
Device (PEGG)
{
Name (_ADR, 0x00020000)
Name (_UID, 0x00)
Name (_BBN, 0x02)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
})
}
Device (PEX0)
{
Name (_ADR, 0x00030000)
Name (_UID, 0x00)
Name (_BBN, 0x03)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
})
}
Device (PEX1)
{
Name (_ADR, 0x00030001)
Name (_UID, 0x00)
Name (_BBN, 0x04)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
})
}
Device (PEX2)
{
Name (_ADR, 0x00030002)
Name (_UID, 0x00)
Name (_BBN, 0x05)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
})
}
Device (PEX3)
{
Name (_ADR, 0x00030003)
Name (_UID, 0x00)
Name (_BBN, 0x06)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
})
}
Device (ISA) {
Name (_ADR, 0x00110000)
/* PS/2 keyboard (seems to be important for WinXP install) */
Device (KBD)
{
Name (_HID, EisaId ("PNP0303"))
Method (_STA, 0, NotSerialized)
{
Return (0x0f)
}
Method (_CRS, 0, NotSerialized)
{
Name (TMP, ResourceTemplate () {
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
IRQNoFlags () {1}
})
Return (TMP)
}
}
/* PS/2 mouse */
Device (MOU)
{
Name (_HID, EisaId ("PNP0F13"))
Method (_STA, 0, NotSerialized)
{
Return (0x0f)
}
Method (_CRS, 0, NotSerialized)
{
Name (TMP, ResourceTemplate () {
IRQNoFlags () {12}
})
Return (TMP)
}
}
/* PS/2 floppy controller */
Device (FDC0)
{
Name (_HID, EisaId ("PNP0700"))
Method (_STA, 0, NotSerialized)
{
Return (0x0f)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () {
IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
IRQNoFlags () {6}
DMA (Compatibility, NotBusMaster, Transfer8) {2}
})
Return (BUF0)
}
}
}
}
}
}
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