227 lines
6.1 KiB
Plaintext
227 lines
6.1 KiB
Plaintext
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# Applies to unbuffered DIMM types
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# UDIMM, SO-DIMM, Micro-DIMM, Micro-UDIMM,
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# 72b-SO-UDIMM, 16b-SO-UDIMM, 32b-SO-UDIMM
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# 4_01_02_11R24.pdf
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#
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# JEDEC Standard No. 21-C
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# Page 4.1.2.11 - 1
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# Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules
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# DDR3 SPD
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# Document Release 6
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# UDIMM Revision 1.3
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# RDIMM Revision 1.3
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# CDIMM Revision 1.3
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# LRDIMM Revision 1.2
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{
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# Byte 0: Number of Bytes Used / Number of Bytes in SPD Device /
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# CRC Coverage
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"SPD_Bytes_Used" : 4,
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"SPD_Bytes_Total" : 3,
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"CRC_Coverage" : 1,
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# Byte 1: SPD Revision
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"SPD_Revision" : 8,
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# Byte 2: Key Byte / DRAM Device Type
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"DRAM_Device_Type" : 8,
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# Byte 3: Key Byte / Module Type
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"Module_Type" : 4,
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"Byte_3_reserved" : 4,
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# Byte 4: SDRAM Density and Banks
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"SDRAM_Capacity" : 4,
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"Bank_Address_Bits" : 3,
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"Byte_4_reserved" : 1,
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# Byte 5: SDRAM Addressing
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"Column_Address_Bits" : 3,
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"Row_Address_Bits" : 3,
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"Byte_5_reserved" : 2,
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# Byte 6: Module Nominal Voltage, VDD
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"NOT_1.5_V_Operable" : 1,
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"1.35_V_Operable" : 1,
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"1.25_V_Operable" : 1,
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"Byte_6_reserved" : 5,
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# Byte 7: Module Organization
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"SDRAM_Device_Width" : 3,
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"Number_of_Ranks" : 3,
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"Byte_7_reserved" : 2,
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# Byte 8: Module Memory Bus Width
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"Primary_Bus_Width" : 3,
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"Bus_Width_Extension" : 3,
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"Byte_8_reserved" : 2,
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# Byte 9: Fine Timebase (FTB) Dividend / Divisor
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"Fine_Timebase_Divisor" : 4,
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"Fine_Timebase_Dividend" : 4,
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# Bytes 10 / 11: Medium Timebase (MTB) Dividend / Divisor
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"Medium_Timebase_Dividend" : 8,
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"Medium_Timebase_Divisor" : 8,
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# Byte 12: SDRAM Minimum Cycle Time (t CK min)
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"Minimum_SDRAM_Cycle_Time" : 8,
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# Byte 13: Reserved
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"Byte_13_Reserved" : 8,
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# Bytes 14 / 15: CAS Latencies Supported
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"CL_4_Supported" : 1,
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"CL_5_Supported" : 1,
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"CL_6_Supported" : 1,
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"CL_7_Supported" : 1,
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"CL_8_Supported" : 1,
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"CL_9_Supported" : 1,
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"CL_10_Supported" : 1,
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"CL_11_Supported" : 1,
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"CL_12_Supported" : 1,
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"CL_13_Supported" : 1,
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"CL_14_Supported" : 1,
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"CL_15_Supported" : 1,
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"CL_16_Supported" : 1,
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"CL_17_Supported" : 1,
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"CL_18_Supported" : 1,
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"Byte_15_Reserved" : 1,
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# Byte 16: Minimum CAS Latency Time (tAAmin)
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"tAAmin" : 8,
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# Byte 17: Minimum Write Recovery Time (tWRmin)
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"tWRmin" : 8,
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# Byte 18: Minimum RAS to CAS Delay Time (tRCDmin)
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"tRCDmin" : 8,
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# Byte 19: Minimum Row Active to Row Active Delay Time (tRRDmin)
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"tRRDmin" : 8,
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# Byte 20: Minimum Row Precharge Delay Time (tRPmin)
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"tRPmin" : 8,
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# Bytes 21 - 23: Minimum Active to Precharge Delay Time (tRASmin)
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# / Minimum Active to Active/Refresh Delay Time
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# (tRCmin)
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"tRASmin_Most_Significant Nibble" : 4,
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"tRCmin_Most_Significant Nibble" : 4,
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"tRASmin_LSB" : 8,
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"tRCmin_LSB" : 8,
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# Bytes 24 - 25: Minimum Refresh Recovery Delay Time (tRFCmin)
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"tRFCmin LSB" : 8,
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"tRFCmin MSB" : 8,
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# Byte 26: Minimum Internal Write to Read Command Delay Time
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"tWTRmin" : 8,
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# Byte 27: Minimum Internal Read to Precharge Command Delay Time
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# (tRTPmin)
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"tRTPmin" : 8,
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# Byte 28 - 29: Minimum Four Activate Window Delay Time
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# (tFAWmin)
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"tFAWmin Most Significant Nibble" : 4,
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"Byte_28_Reserved" : 4,
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"tFAWmin Most Significant Byte" : 8,
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# Byte 30: SDRAM Optional Features
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"RQZ_Div_6_Supported" : 1,
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"RQZ_Div_7_Supported" : 1,
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"Byte_30_Reserved" : 5,
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"DLL_Off_Mode_Supported" : 1,
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# Byte 31: SDRAM Thermal and Refresh
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# Options
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"Extended_Temp_range_supported" : 1,
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"Extended_Temp_Refresh_1x_Refresh" : 1,
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"Auto_Self_Refresh_Supported" : 1,
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"On-Die_Thermal_Sensor" : 1,
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"Byte_31_Reserved" : 3,
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"Partial_Array_Self_Refresh_Supported" : 1,
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# Byte 32: Module Thermal Sensor
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"Thermal_Sensor_Accuracy" : 7,
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"Thermal_Sensor_incorporated" : 1,
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# Byte 33: SDRAM Device Type
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"Signal_Loading" : 2,
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"Byte_33_Reserved" : 2,
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"Die_Count" : 3,
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"SDRAM_Device_Type" : 1,
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# Byte 34: Fine Offset for SDRAM Minimum
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# Cycle Time (tCKmin)
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"tCKmin_Fine_Offset" : 8,
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#Byte 35: Fine Offset for Minimum CAS Latency Time (tAAmin)
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"tAAmin_Fine_Offset" : 8,
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# Byte 36: Fine Offset for Minimum RAS to CAS Delay Time
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# (tRCDmin)
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"tRCDmin_Fine_Offset" : 8,
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#Byte 37: Fine Offset for Minimum Row Precharge Delay Time
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# (tRPmin)
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"tRPmin_Fine_Offset" : 8,
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# Byte 38: Fine Offset for Minimum Active to Active/Refresh
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# Delay Time (tRCmin)
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"tRCmin_Fine_Offset" : 8,
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# Bytes 39 / 40: Reserved
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"Byte_39_Reserved" : 8,
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"Byte_40_Reserved" : 8,
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# Byte 41: SDRAM Maximum Active Count (MAC) Value
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"Maximum_Activate_Count" : 4,
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"Maximum_Activate_Window" : 2,
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"Byte_41_Reserved" : 2,
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# Bytes 42 - 59: Reserved
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"Reserved_bytes_42_to_59_" [18] : 8,
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# Module-Specific Section: Bytes 60 - 116 for Unbuffered DIMMS
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# Byte 60 (Unbuffered): Raw Card Extension, Module Nominal Height
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"Module_Nominal_Height" : 5,
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"Raw_Card_Estension" : 3,
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# Byte 61 (Unbuffered): Module Maximum Thickness
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"Module_Thickness_Front" : 4,
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"Module_Thickness_Back" : 4,
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# Byte 62 (Unbuffered): Reference Raw Card Used
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"Reference_Raw_Card" : 5,
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"Reference_Raw_Card_Revision" : 2,
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"Reference_Raw_Card_Extension" : 1,
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# Byte 63: Address Mapping from Edge Connector to DRAM
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"Rank_1_Mapping_Mirrored" : 1,
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"Byte_63_Reserved" : 7,
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# Bytes 64 -116 (Unbuffered): Reserved
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"Module_Specific_Byte_Reserved_"[53] : 8,
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# Bytes 117 - 118: Module ID: Module Manufacturers JEDEC ID Code
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"Module_Manufacturer_JEDEC_ID_Code" : 16,
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# Byte 119: Module ID: Module Manufacturing Location
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"Module_Manufacturing_Location" : 8,
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# Bytes 120 - 121: Module ID: Module Manufacturing Date
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"Module_Manufacturing_Date" : 16,
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# Bytes 122 - 125: Module ID: Module Serial Number
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"Module_Serial_Number" : 32,
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# Bytes 126 - 127: Cyclical Redundancy Code
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"Module_CRC" : 16
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}
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