55 lines
1.3 KiB
Text
55 lines
1.3 KiB
Text
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config SOUTHBRIDGE_INTEL_LYNXPOINT
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bool
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if SOUTHBRIDGE_INTEL_LYNXPOINT
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config SOUTH_BRIDGE_OPTIONS # dummy
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def_bool y
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select IOAPIC
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select HAVE_HARD_RESET
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select HAVE_USBDEBUG
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select USE_WATCHDOG_ON_BOOT
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select SPI_FLASH
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config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/lynxpoint/bootblock.c"
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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help
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If you set this option to y, the serial IRQ machine will be
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operated in continuous mode.
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endif
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