2020-10-22 14:03:46 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2020-10-22 14:13:14 +02:00
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <console/console.h>
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2020-10-22 14:03:46 +02:00
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#include <device/pci_ops.h>
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#include <cpu/x86/smm.h>
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#include <soc/pci_devs.h>
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void smm_region(uintptr_t *start, size_t *size)
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{
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uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR);
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uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR);
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tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB);
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tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB);
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/* Only the upper [31:20] bits of an address are checked against
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* VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this
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* effectively means +1MiB for the limit.
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*/
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tseg_limit += 1 * MiB;
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*start = tseg_base;
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*size = tseg_limit - tseg_base;
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}
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2020-10-22 14:13:14 +02:00
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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/*
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* We need to make sure ramstage will be run cached. At this
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* point exact location of ramstage in cbmem is not known.
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* Instruct postcar to cache 16 megs under cbmem top which is
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* a safe bet to cover ramstage.
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*/
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uintptr_t top_of_ram = (uintptr_t)cbmem_top();
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printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
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top_of_ram -= 16 * MiB;
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postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK);
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/* Cache the TSEG region */
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if (CONFIG(TSEG_STAGE_CACHE))
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postcar_enable_tseg_cache(pcf);
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}
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