99 lines
3.5 KiB
ArmAsm
99 lines
3.5 KiB
ArmAsm
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/*
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* Optimized assembly for low-level CPU operations on ARM64 processors.
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*
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* Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
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* Copyright (c) 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/asm.h>
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.macro dcache_apply_all crm
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dsb sy
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mrs x0, clidr_el1 // read CLIDR
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and w3, w0, #0x07000000 // narrow to LoC
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lsr w3, w3, #23 // left align LoC (low 4 bits)
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cbz w3, 5f //done
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mov w10, #0 // w10 = 2 * cache level
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mov w8, #1 // w8 = constant 0b1
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1: //next_level
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add w2, w10, w10, lsr #1 // calculate 3 * cache level
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lsr w1, w0, w2 // extract 3-bit cache type for this level
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and w1, w1, #0x7 // w1 = cache type
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cmp w1, #2 // is it data or i&d?
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b.lt 4f //skip
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msr csselr_el1, x10 // select current cache level
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isb // sync change of csselr
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mrs x1, ccsidr_el1 // w1 = read ccsidr
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and w2, w1, #7 // w2 = log2(linelen_bytes) - 4
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add w2, w2, #4 // w2 = log2(linelen_bytes)
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ubfx w4, w1, #3, #10 // w4 = associativity - 1 (also
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// max way number)
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clz w5, w4 // w5 = 32 - log2(ways)
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// (bit position of way in DC)
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lsl w9, w4, w5 // w9 = max way number
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// (aligned for DC)
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lsl w16, w8, w5 // w16 = amount to decrement (way
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// number per iteration)
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2: //next_way
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ubfx w7, w1, #13, #15 // w7 = max set #, right aligned
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lsl w7, w7, w2 // w7 = max set #, DC aligned
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lsl w17, w8, w2 // w17 = amount to decrement (set
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// number per iteration)
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3: //next_set
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orr w11, w10, w9 // w11 = combine way # & cache #
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orr w11, w11, w7 // ... and set #
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dc \crm, x11 // clean and/or invalidate line
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subs w7, w7, w17 // decrement set number
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b.ge 3b //next_set
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subs x9, x9, x16 // decrement way number
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b.ge 2b //next_way
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4: //skip
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add w10, w10, #2 // increment 2 *cache level
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cmp w3, w10 // Went beyond LoC?
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b.gt 1b //next_level
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5: //done
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dsb sy
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isb
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ret
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.endm
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ENTRY(dcache_invalidate_all)
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dcache_apply_all crm=isw
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ENDPROC(dcache_invalidate_all)
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ENTRY(dcache_clean_all)
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dcache_apply_all crm=csw
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ENDPROC(dcache_clean_all)
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ENTRY(dcache_clean_invalidate_all)
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dcache_apply_all crm=cisw
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ENDPROC(dcache_clean_invalidate_all)
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